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Power/Performance Bits: Feb. 23


Photonic AI accelerator There are now many processors and accelerators focused on speeding up neural network performance, but researchers at the University of Münster, University of Oxford, Swiss Federal Institute of Technology Lausanne (EPFL), IBM Research Europe, and University of Exeter say AI processing could happen even faster with the use of photonic tensor processors that can handle mu... » read more

Testing Silicon Photonics In Production


As silicon photonics costs come down, the technology is being worked into new applications, from connectivity to AI. But full commercial production requires testing those photonic circuits before shipping them. Photonics testing is only getting started. Volume production is still not happening, and test equipment and techniques are still being developed. What exists today is a blend of exist... » read more

Attaching Fibers To Photonic Chips


Recently, Cadence held its fifth photonics summit, CadenceCONNECT: Photonics Contribution to High-Performance Computing. You can read my earlier posts: Photonic Integration—From Switching to Computing How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs The third day was all about how to connect the incoming and outgoing fibers to the photonics chips. I will cov... » read more

Power/Performance Bits: Nov. 17


NVMe controller for research Researchers at the Korea Advanced Institute of Science and Technology (KAIST) developed a non-volatile memory express (NVMe) controller for storage devices and made it freely available to universities and research institutions in a bid to reduce research costs. Poor accessibility of NVMe controller IP is hampering academic and industrial research, the team argue... » read more

Blog Review: Nov. 4


Arm's Joshua Sowerby points to how to improve machine learning performance on mobile devices by using smart pruning to remove convolution filters from a network, reducing its size, complexity, and memory footprint. Mentor's Neil Johnson checks out how designers can write and verify RTL real-time using formal property checking in the style of test-driven development and why to give it a try. ... » read more

Startup Funding: October 2020


October 2020 was a big month for startups across the automotive space, with sizeable funding all around. Three startups based out of China brought in over $100M apiece for ADAS and autonomous driving, and a fourth U.S.-based startup saw $125M investment for simulating and testing autonomous driving systems. Two electric vehicle manufacturers also received $100M+ rounds. Collectively, the auto c... » read more

Power/Performance Bits: Oct. 20


Benchmarking quantum layout synthesis Computer scientists at the University of California Los Angeles found that current compilers for quantum computers are inhibiting optimal performance and argue that better quantum compilation design could help improve computation speeds up to 45 times. The team designed a family of benchmark quantum circuits with known optimal depths or sizes, which cou... » read more

Power/Performance Bits: Sept. 15


Higher-res lidar Researchers from Purdue University and École Polytechnique Fédérale de Lausanne (EPFL) devised a way to improve lidar and provide higher-resolution detection of nearby fast-moving objects through mechanical control and modulation of light on a silicon chip. "Frequency modulated continuous wave" (FMCW) lidar detects objects by scanning laser light from the top of a vehicl... » read more

Power/Performance Bits: Sept. 9


Smaller, cheaper integrated photonics Researchers from the University of California Santa Barbara, California Institute of Technology (Caltech), and Ecole Polytechnique Fédérale de Lausanne (EPFL) developed a way to integrate an optical frequency comb on a silicon photonic chip. Optical frequency combs are collections of equally spaced frequencies of laser light (so called because when pl... » read more

New Architectures, Much Faster Chips


The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

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