UCIe-3D: SiP Architectures With Advanced 3D Packaging With Shrinking Bump Pitches (Intel)


A technical paper titled “High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express” was published by researchers at Intel.


“Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0 specification defines interoperability using standard and advanced packaging technologies with planar interconnects. Here we examine the development of UCIe as the bump interconnect pitches reduce with advances in packaging technologies for three-dimensional integration of chiplets. We report a die-to-die solution for the continuum of package bump pitches down to 1 µm, providing circuit architecture details and performance results. Our analysis suggests that—contrary to trends seen in traditional signalling interfaces—the most power-efficient performance for these architectures can be achieved by reducing the frequency as the bump pitch goes down. Our architectural approach provides power, performance and reliability characteristics approaching or exceeding that of a monolithic system-on-chip design as the bump pitch approaches 1 µm.”

Find the technical paper here. Published February 2024.

Das Sharma, D., Pasdast, G., Tiagaraj, S. et al. High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express. Nat Electron (2024). https://doi.org/10.1038/s41928-024-01126-y

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