UCIe-3D: SiP Architectures With Advanced 3D Packaging With Shrinking Bump Pitches (Intel)

A technical paper titled “High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express” was published by researchers at Intel. Abstract: "Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0... » read more

Why Use A Package?

Subramanian Iyer, distinguished chancellor's professor in UCLA's Electrical Engineering Department—and a former fellow and director of the systems scaling technology department at IBM—sat down with Semiconductor Engineering to talk about the future of chip scaling. What follows are excerpts of that conversation. SE: Advanced packaging is being viewed as a way to extend scaling in the fut... » read more