中文 English

Expanding Silicon Lifecycle Management To Real-Time System Performance Optimization


Semiconductor development is currently in one of its periodic crises, with many factors combining to require dramatically new technologies and methodologies. Chips continue to grow ever larger and more complex, with 3D IC devices adding another layer of challenges. Huge data centers, autonomous vehicles, and algorithms using artificial intelligence (AI) and machine learning (ML) drive a relentl... » read more

Manage Scaling Challenges For Silicon Success


Semiconductor companies are faced with significant challenges related to technology scaling, design scaling, and system scaling. These challenges have a broad impact on design development, manufacturing, and functional operation. This paper discusses the challenges and the specific impact of a Silicon Lifecycle Solutions approach that includes DFT, operations, and Embedded Analytics in enabling... » read more

SLM Is Changing The Complete Device Lifecycle Process


Amit Sanghani, Vice President of Engineering, HW-Analytics and Test Group at Synopsys, discusses how Silicon Lifecycle Management (SLM) is changing the way we look at the complete device lifecycle process and how it can enable heightened levels of visibility in device performance, reliability and security. Learn how SLM is well placed to address the challenges that occur at every stage of cut... » read more

Securing The SoC Life Cycle


Over the course of its life, an SoC (system on chip) goes through multiple life cycle states which are different in character and have varying and sometimes contradictory security requirements. In each state, the SoC may be under different ownership in the supply chain. Also, as it transitions through different manufacturing phases, it is subject to a different set of possible attacks, which sh... » read more

Reliability Costs Becoming Harder To Track


Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

The Good And Bad Of Auto IC Updates


Keeping automobiles updated enough to avoid problems is becoming increasingly difficult as more complex electronics are added into vehicles, and as the lifetimes of those devices are extended to a decade or more. Modern vehicles are full of electronics. In fact, the value of electronic devices used in modern vehicles is expected to double in the next 10 years, growing to $469 billion by 2030... » read more

One-On-One: Lip-Bu Tan


Lip-Bu Tan, CEO of Cadence, sat down with Semiconductor Engineering to talk about the impact of massive increases in data across a variety of industries, the growing need for computational software, and the potential implications of U.S.-China relations. What follows are excerpts of that discussion. SE: What do you see as the biggest change for the chip industry? Tan: We're in our fifth g... » read more

Power Optimization: What’s Next?


Concerns about the power consumed by semiconductors has been on the rise for the past couple of decades, but what can we expect to see coming in terms of analysis and automation from EDA companies, and is the industry ready to make the investment? Ever since Dennard scaling stopped providing automatic power gains by going to a smaller geometry, circa 2006, semiconductors have been increasing... » read more

Testing Analog Circuits Becoming More Difficult


Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

Merging Verification And Test


While the disciplines of functional verification and test serve different purposes, their histories were once closely intertwined. Recent safety and security monitoring requirements coupled with capabilities being embedded into devices is bringing them closer together again, but can they successfully cooperate to bring about improvements in both? Getting there may be difficult. Three phases ... » read more

← Older posts