AI Accelerator Testing Depends On DFT Innovations

By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

HBM Shifts Testing Left To Preserve AI Chip Yield

By Anne Meixner - 12 May, 2026 - Comments: 1

Key Takeaways: A high-yield, known-good stack requires multiple test insertions. Known good stack testing poses challenges for power delivery and thermal management. The shift to HBM4 and HBM5 will increase the pressure for shift-left test flows. Taller high-bandwidth memory (HBM) stacks and tighter TSV pitch are impacting AI module yields. The solution is to push test furth... » read more

What’s Failing At The Interface

By Gregory Haley - 07 Apr, 2026 - Comments: 0

Key Takeaways The interface is where failures in advanced packaging become visible, but it's increasingly not where they originate. Weak interfaces often don't fail at time zero, but they do degrade due to parametric drift and margin erosion that binary test screens miss entirely. The temporary test interconnect is the largest variable in the measurement chain and must be controlled ... » read more

Framework for Optimizing Reliability and Thermal Management of 3DICs (National Taiwan Univ., Lamar Univ.)

By Technical Paper Link - 10 Oct, 2025 - Comments: 0

A new technical paper titled "The Impact of Process Variations on the Thermo-Mechanical Behavior of 3D Integrated Circuits" was published by researchers at National Taiwan University and Lamar University. Abstract "The use of vertically stacked architectures in three-dimensional integrated circuits (3DICs) offers a transformative path for advancing Moore’s Law by significantly boosting co... » read more

Monolithic Integration of Air-Clad Optical Through-Silicon Waveguides in Silicon (TH Wildau et al.)

By Technical Paper Link - 08 Oct, 2025 - Comments: 0

A new technical paper titled "Monolithically Integrated Optical Through-Silicon Waveguides for 3D Chip-to-Chip Photonic Interconnects" was published by researchers at the Technical University of Applied Sciences Wildau, TU of Applied Sciences Mittelhessen, TU Ilmenau, Brandenburg University of Technology and Fraunhofer IPMS. Abstract "The scaling limitations of electrical interconnects are ... » read more

Transformation Of 2D-ICs Into 3D-ICs Using Shuttle Chips From Multi-Project Wafers (Tohoku University)

By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "Die-Level Transformation of 2D Shuttle Chips into 3D-IC for Advanced Rapid Prototyping using Meta Bonding" was published by researchers at Tohoku University. Abstract "Three-dimensional integrated circuit (3D-IC) technology, often referred to as through-silicon via (TSV) formation technology, has been steadily maturing and is increasingly used in advanced semic... » read more

What’s Next For Through-Silicon Vias

By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Complex Heterogeneous Integration Drives Innovation In Semiconductor Test

By Jeorge Hurtarte - 15 Oct, 2024 - Comments: 0

Heterogeneous integration is driving innovation in the semiconductor industry, but it also introduces more complexity in chip design, which translates to more intricate test requirements. The automated test equipment (ATE) industry is responding, developing and utilizing more sophisticated test equipment capable of handling the diverse functionalities and interfaces needed to test heterogeneous... » read more

Overview of Test Strategies for 3DICs

By Technical Paper Link - 26 Jun, 2024 - Comments: 0

A new technical paper titled "Design-for-Test Solutions for 3D Integrated Circuits" was published by researchers at Duke University, Arizona State University, and NVIDIA. Abstract: "As Moore's Law approaches its limits, 3D integrated circuits (ICs) have emerged as promising alternatives to conventional scaling methodologies. However, the benefits of 3D integration in terms of lower power co... » read more

Impact of CMOS Image Sensors Fabrication Processes On The Quality Of Smartphone Pictures

By Technical Paper Link - 06 Jul, 2023 - Comments: 0

A technical paper titled “A Review of the Recent Developments in the Fabrication Processes of CMOS Image Sensors for Smartphones” was published by researchers at Texas A&M University. Abstract: "CMOS Image Sensors are experiencing significant growth due to their capabilities to be integrated in smartphones with refined image quality. One of the major contributions to the growth of ima... » read more

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tag: TSV