Heterogeneous IC Packaging: Optimizing Performance And Cost

Choice of packaging technology is influenced by the communication interface between chiplets.


Leading integrated circuit (IC) foundries are already shipping 7-nm and 5-nm wafers and 3-nm product qualifications are ongoing. Wafer costs continue to soar as high transistor density requires ever more expensive processes to fabricate them. Even if defect densities can remain relatively flat as new nodes emerge, the cost per unit area of silicon increases nonlinearly. These economics have placed a new packaging technology squarely into the discussions for future product architectures.

The amazing transistor densities and clock speeds afforded by new silicon nodes are being considered for functional applications where performance is paramount. But what about all the other areas of a typical high-performance die that do not need to be on the latest silicon node for improved performance?

Heterogeneous packaging has been the industry’s answer, enabling a design approach that has been the holy grail for a long time but only recently has become practical. Portions of what would have been a single-die, system on chip (SoC), are being carved out of the homogenous designs and created in smaller independent silicon die. The first trend has been to remove the input/output I/O blocks that communicate to the memory and long reach serial/deserializer (SerDes) types as well.

This creates an electrical, functional, physical building block landscape whereby IC functional blocks can be qualified and reused over and over. Spreading the original investments over a larger number of end devices in this manner was nearly unthinkable just a few years ago.

The industry got started on this most recent evolution with 2.5D Through Silicon Via (TSV) products, which allow very high-density DRAM memories or High Bandwidth Memory (HBM) to be implemented alongside the application-specific IC (ASIC) in the same IC package. Now, as functional blocks, these circuit items are being removed from SoCs. Examples include central processing units (CPUs) as stand-alone silicon chiplets, and GPUs, general compute and high-speed IO blocks, to mention a few.

To address these offerings, several key technologies have been developed for integrating a few, or many, die into a high-performance collection of discrete die whether it is logic or memory or other. These developments include high-density multi-die offerings utilizing conventional package substrates, the so-called multichip module (MCM) Flip Chip ball grid array (FCBGA), as well as very fine-line constructions such as 2.5D TSV and High-Density Fan-Out (HDFO) offerings. New chiplet integrations using substrate SWIFT (S-SWIFT) technology is now being qualified. S-SWIFT HDFO solutions permit fine line routing down to 2-µm line and 2-µm space and 6-layer construction. This module fabrication technology has been developed over the last 3 years and upgraded to realistically permit the integration of chiplets and HBM memories. S-Connect is combined HDFO and bridge offering which is in the internal qualification phase.

The choice of which IC packaging technology to implement for a heterogeneous construction using chiplets is heavily influenced by the communication interface between chiplets, see figure 1. High speed parallel interfaces with 100s or 1000s of IO between die are preferred for many applications, and this requires a high-density interconnect, such as 2.5D TSV which uses a silicon interposer or High-Density Fan-Out (HDFO S-SWIFT), or a bridge technology (S-Connect).

Fig. 1: Die-to-die interface selection.

S-SWIFT utilizes Cu fine line photolithography and organic dielectrics to achieve a high level of signal routing density, fabricated on-site. S-Connect uses this same high-density RDL technology more sparingly but adds high density bridges to aid in the extreme high-density routing between chiplets. 3D die stacking using ultra dense vertical die-to-die interconnections afforded by Cu hybrid bonding will compliment the 2D integrations also in the future.


The future of these packaging technologies is bright. New product designs for 2D integrations of chiplets have increased 4-fold in just the last year. Improved silicon architectural flexibility, chiplet reuse, reduced time-to-market, and lower overall cost continues to drive this innovation in the packaging industry as Amkor continues to deliver advances in the heterogenous IC packaging roadmap.

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