Chip Industry Week in Review


The IEEE ISSCC conference was held this week in San Francisco. Among the highlights: IBM detailed an AI accelerator based on its new inferencing dataflow architecture. CEA-Leti presented a chip-scale, ultra-fast, battery-operated EPR spectrometer. QuTech introduced a cryo-CMOS SoC with NV centers in diamond. UTokyo showed its low-jitter PLL architecture for beyond 5G/6G. Imec d... » read more

Why Indium Oxide Chips Are Getting So Much Attention


Key Takeaways Their low leakage is of interest for memory applications, particularly capacitor-less gain cell designs; They can be deposited over large areas using low-temperature processes, a very desirable characteristic for BEOL integration, and The variety of compositions available gives designers many options to achieve the specific properties they need. Indium tin oxide (ITO), ... » read more

Chip Industry Week In Review


TSMC is expected to reduce its Fab 14 mature-node capacity by 15% to 20% to free up resources for its advanced packaging technologies, reports Counterpoint. The foundry will likely rely on its VIS affiliate site in Singapore (operational in late 2026) and other overseas fabs to ensure continued supply for older nodes. Memory The U.S. threatened 100% tariffs on South Korean memory compan... » read more

A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)


A new technical paper titled "Memory DisOrder: Memory Re-orderings as a Timerless Side-channel" was published by researchers at University of Washington, Duke University, UC Santa Cruz, Raytheon and Microsoft Research. Abstract "To improve efficiency, nearly all parallel processing units (CPUs and GPUs) implement relaxed memory models in which memory operations may be re-ordered, i.e., ex... » read more

Chip Industry Technical Paper Roundup: Oct. 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=484 /] Find more semiconductor research papers here. » read more

Statistical Model Checking As An Evaluation Tool of Microarchitectural Side Channels (Duke, Harvard, Univ. of Florida)


A new technical paper titled "Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking" was published by researchers at Duke University, Harvard University and University of Florida. Abstract "Rigorous quantitative evaluation of microarchitectural side channels is challenging for two reasons. First, the processors, attacks, and defenses often exhibit probabili... » read more

Chip Industry Technical Paper Roundup: August 19


New technical papers recently added to Semiconductor Engineering’s library: [table id=465 /] Find more semiconductor research papers here. » read more

Microservice-Based LLM Agents Enable EDA Flow Automation (Duke Univ. and Univ. of Maryland)


A new technical paper titled "AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agents" was published by researchers at Duke University and University of Maryland. Abstract "Modern Electronic Design Automation (EDA) workflows, especially the RTL-to-GDSII flow, require heavily manual scripting and demonstrate a multitude of tool-specific interactions which limits scalabili... » read more

Chip Industry Technical Paper Roundup: July 15


New technical papers recently added to Semiconductor Engineering’s library: [table id=446 /] Find more semiconductor research papers here. » read more

LLM-Powered Automatic VLSI Design Flow Tuning Framework


A new technical paper titled "CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs" was published by researchers at Duke University and Synopsys. Abstract "Modern very large-scale integration (VLSI) design requires the implementation of integrated circuits using electronic design automation (EDA) tools. Due to the complexity of EDA algorithms, the vast parameter space... » read more

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