Reliability Over Time And Space


The demand for known good die is well understood as multi-chip packages are used in safety-critical and mission-critical applications, but that alone isn't sufficient. As chips are swapped in and out of packages to customize them for specific applications, it will be the entire module that needs to be verified, simulated and tested, and analyzed. This is more complicated than it sounds for s... » read more

Problems And Solutions In Analog Design


Advanced chip design is becoming a great equalizer for analog and digital at each new node. Analog IP has more digital circuitry, and digital designs are more susceptible to kinds of noise and signal disruption that have plagued analog designs for years. This is making the design, test and packaging of SoCs much more complicated. Analog components cause the most chip production test failures... » read more

The Race To Much More Advanced Packaging


Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

Advanced Packaging Makes Testing More Complex


The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

Moore And More


For more than 50 years, the semiconductor industry has enjoyed the benefits of Moore's Law — or so it seemed. In reality, there were three laws rolled up into one: Each process generation would have a higher clock speed at the same power. This was not discovered by Moore, but by Dennard, who also invented the DRAM. Process generations continue to get faster and lower power, but the power... » read more

2.5D, 3D Power Integrity


Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of diffe... » read more

Advanced Packaging’s Progress


Shim Il Kwon, CTO at STATS ChipPAC, sat down with Semiconductor Engineering to discuss the current and future trends of chip packaging. What follows are excerpts of that conversation. SE: The outsourced semiconductor assembly and test (OSAT) vendors provide third-party IC-packaging and test services. What are the big challenges for OSATs today? Shim: The OSAT market is very competitive, w... » read more

Is The Stacked Die Ecosystem Stagnating?


It is now widely agreed that not much has been happening in terms of adoption for 2.5D interposer and 3D ICs. “It seems like everyone is still at the starting line waiting for the race to begin," said Javier DeLaCruz, senior director of engineering of [getentity id="22242" e_name="eSilicon"]. "Interposer assembly and IP availability for effectively using the [getkc id="82" comment="2.5D IC... » read more

More Than Moore


Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

When Will 2.5D Cut Costs?


There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

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