Front-end patterning and epitaxy approach on Si photonics 220nm SOI substrates


A new technical paper titled “Lateral Tunnel Epitaxy of GaAs in Lithographically Defined Cavities on 220 nm Silicon-on-Insulator” was published by researchers at Cardiff University and University of Southampton.


“Current heterogeneous Si photonics usually bond III–V wafers/dies on a silicon-on-insulator (SOI) substrate in a back-end process, whereas monolithic integration by direct epitaxy could benefit from a front-end process where III–V materials are grown prior to the fabrication of passive optical circuits. Here we demonstrate a front-end-of-line (FEOL) processing and epitaxy approach on Si photonics 220 nm (001) SOI wafers to enable positioning dislocation-free GaAs layers in lithographically defined cavities right on top of the buried oxide layer. Thanks to the defect confinement in lateral growth, threading dislocations generated from the III–V/Si interface are effectively trapped within ∼250 nm of the Si surface. This demonstrates the potential of in-plane co-integration of III–Vs with Si on mainstream 220 nm SOI platform without relying on thick, defective buffer layers. The challenges associated with planar defects and coalescence into larger membranes for the integration of on-chip optical devices are also discussed.”

Find the technical paper here. Published October 2023.

Zhao Yan, Bogdan-Petrin Ratiu, Weiwei Zhang, Oumaima Abouzaid, Martin Ebert, Graham T. Reed, David J. Thomson, and Qiang Li
Crystal Growth & Design 2023 23 (11), 7821-7828
DOI: 10.1021/acs.cgd.3c00633

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