Silicon Photonics Manufacturing Ramps Up

Circuit scaling is starting to hit a wall as the laws of physics clash with exponential increases in the volume of data, forcing chipmakers to take a much closer look at silicon photonics as a way of moving data from where it is collected to where it is processed and stored. The laws of physics are immutable. Put simply, there are limits to how fast an electron can travel through copper. The... » read more

Front-end patterning and epitaxy approach on Si photonics 220nm SOI substrates

A new technical paper titled "Lateral Tunnel Epitaxy of GaAs in Lithographically Defined Cavities on 220 nm Silicon-on-Insulator" was published by researchers at Cardiff University and University of Southampton. Abstract "Current heterogeneous Si photonics usually bond III–V wafers/dies on a silicon-on-insulator (SOI) substrate in a back-end process, whereas monolithic integration by di... » read more

New Architecture Elements For 5G RF Front-End Modules To Reduce Noise, Improve Efficiency, And Allow Multiple Radio Transmitters

A technical paper titled “Circuits for 5G RF front-end modules” was published by researchers at Skyworks Solutions Inc. Abstract: "Worldwide adoption of fourth-generation wireless (4G) long-term evolution (LTE) smartphones and the actual transition to fifth-generation wireless (5G) is the main driving engine for semiconductor industry. 5G is expected to reach high data rate speeds (1 Gbps... » read more

How A Highly Controllable SDE Can Be Achieved In A Josephson Junction Where The Normal Section Is A Magnetic Racetrack 

A technical paper titled “Josephson transistor from the superconducting diode effect in domain wall and skyrmion magnetic racetracks” was published by researchers at University of Basel. Abstract: "In superconductors, the combination of broken time-reversal and broken inversion symmetries can result in a critical current being dependent on the direction of current flow. This phenomenon is... » read more

Novel Multi-Independent Gate-Controlled FinFET Technology

A new technical paper titled "Characteristics of a Novel FinFET with Multi-Enhanced Operation Gates (MEOG FinFET)" was published by researchers at Changzhou University. Abstract: "This study illustrates a type of novel device. Integrating fin field-effect transistors (FinFETs) with current silicon-on-insulator (SOI) wafers provides an excellent platform to fabricate advanced specific device... » read more

Fully CMOS-compatible Ternary Inverter with a Memory Function Using Silicon Feedback Field-Effect Transistors (FBFETs)

New technical paper titled "New ternary inverter with memory function using silicon feedback field-effect transistors" was published from researchers at Korea University. Abstract: In this study, we present a fully complementary metal–oxide–semiconductor-compatible ternary inverter with a memory function using silicon feedback field-effect transistors (FBFETs). FBFETs operate with a pos... » read more

Flip-Chip Integration of a GaSb Semiconductor Optical Amplifier with a Silicon Photonic Circuit

New research paper titled "Hybrid silicon photonics DBR laser based on flip-chip integration of GaSb amplifiers and µm-scale SOI waveguides" by researchers at Tampere University (Finland). Abstract: "The development of integrated photonics experiences an unprecedented growth dynamic, owing to accelerated penetration to new applications. This leads to new requirements in terms of functional... » read more

Silicon Thermo-Optic Switches with Graphene Heaters Operating at Mid-Infrared Waveband

Abstract "The mid-infrared (MIR, 2–20 μm) waveband is of great interest for integrated photonics in many applications such as on-chip spectroscopic chemical sensing, and optical communication. Thermo-optic switches are essential to large-scale integrated photonic circuits at MIR wavebands. However, current technologies require a thick cladding layer, high driving voltages or may introduce h... » read more

Label-Free C-Reactive Protein Si Nanowire FET Sensor Arrays With Super-Nernstian Back-Gate Operation

Abstract: "We present a CMOS-compatible double gate and label-free C-reactive protein (CRP) sensor, based on silicon on insulator (SOI) silicon nanowires arrays. We exploit a reference subtracted detection method and a super-Nernstian internal amplification given by the double gate structure. We overcome the Debye screening of charged CRP proteins in solutions using antibodies fragments as c... » read more

Thinner Channels With 2D Semiconductors

Moving to future nodes will require more than just smaller features. At 3/2nm and beyond, new materials are likely to be added, but which ones and exactly when will depend upon an explosion of material science research underway at universities and companies around the globe. With field-effect transistors, a voltage applied to the gate creates an electric field in the channel, bending the ban... » read more

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