Research Bits: June 4


Ultra-pure silicon Researchers from the University of Manchester and University of Melbourne developed a technique to engineer ultra-pure silicon that could be used in the construction of high-performance qubit devices that extend quantum coherence times. The highly purified silicon chips house and protect the qubits so they can sustain quantum coherence much longer, enabling complex calcul... » read more

Comparing Thermal Properties In Molybdenum Substrate To Si And Glass For A System-On-Foil Integration (RIT, Lux)


A technical paper titled “Comparative Analysis of Thermal Properties in Molybdenum Substrate to Silicon and Glass for a System-on-Foil Integration” was published by researchers at Rochester Institute of Technology and Lux Semiconductors. Abstract: "Advanced electronics technology is moving towards smaller footprints and higher computational power. In order to achieve this, advanced packag... » read more

Enabling Advanced Devices With Atomic Layer Processes


Atomic layer deposition (ALD) used to be considered too slow to be of practical use in semiconductor manufacturing, but it has emerged as a critical tool for both transistor and interconnect fabrication at the most advanced nodes. ALD can be speeded up somewhat, but the real shift is the rising value of precise composition and thickness control at the most advanced nodes, which makes the ext... » read more

Front-end patterning and epitaxy approach on Si photonics 220nm SOI substrates


A new technical paper titled "Lateral Tunnel Epitaxy of GaAs in Lithographically Defined Cavities on 220 nm Silicon-on-Insulator" was published by researchers at Cardiff University and University of Southampton. Abstract "Current heterogeneous Si photonics usually bond III–V wafers/dies on a silicon-on-insulator (SOI) substrate in a back-end process, whereas monolithic integration by di... » read more

Four Vertical Power Delivery Architectures For Emerging Packaging and Integration Platforms (UIC)


A technical paper titled “Vertical Power Delivery for Emerging Packaging and Integration Platforms – Power Conversion and Distribution” was published by researchers at University of Illinois Chicago. Abstract: "Efficient delivery of current from PCB to point-of-load (POL) is a primary concern in modern high-power high-density integrated systems. Traditionally, a 48 V power signal is con... » read more

Revolution In Embedded Security


The growth of computing, graphics, neural processing power, communication bandwidth, and storage capacities have enabled amazing solutions. These innovations have created great value for society, and that value must be protected from exploitation by adversaries. This whitepaper explores many of these major technology changes and how Rambus’ security offerings help in tackling the new embedded... » read more

Technology Advancements For Dynamic Function eXchange In Vivado ML Edition


As systems become more complex and designers are asked to do more with less, adaptability is a critical asset. While Xilinx FPGAs and SoCs always provided the flexibility to perform on-site device reprogramming, current constraints including increased cost, tighter board space, and power consumption demand even more efficient design strategies. Xilinx Dynamic Function eXchange (DFX) extends the... » read more

X-ray Imaging of Silicon Die Within Fully Packaged Semiconductor Devices


Abstract: "X-ray diffraction imaging (XRDI) (topography) measurements of silicon die warpage within fully packaged commercial quad-flat no-lead devices are described. Using synchrotron radiation, it has been shown that the tilt of the lattice planes in the Analog Devices AD9253 die initially falls, but after 100 °C, it rises again. The twist across the die wafer falls linearly with an incre... » read more

Defect Mitigation And Characterization In Silicon Hardmask Materials


From SPIE Digital Library: In this study, metal contaminants, liquid particle count and on-wafer defects of Si- HMs and filtration removal rates are monitored to determine the effect of filter type, pore size, media morphology, and cleanliness on filtration performance. 5-nm PTFE NTD2 filter having proprietary surface treatment used in this study shows lowest defect count. Authors: Vineet... » read more

Development Of Planarizing Spin-On Carbon Materials For High-Temperature Processes


Multilayer lithography is used for advanced semiconductor processes to pattern complex structures. As more and more procedures incorporate a high-temperature process, such as chemical vapor deposition (CVD), the need for thermally stable materials increases. For certain applications, a spin-on carbon (SOC) layer under the CVD layer is required to survive through a high-temperature process. ... » read more

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