3D In-Memory Compute Making Progress

Researchers at VLSI Symposium looks to indium oxides for BEOL device integration.


Indium compounds are showing great promise for 3D in-memory compute and RF integration, but more work is needed.

Researchers continue to make headway into 3D device integration particularly with indium tin oxide (ITO), which is widely used in display manufacturing. Recent work indicates that different compounds of indium oxide doped with tin, gallium, or zinc combinations may boost transistor characteristics like high carrier mobility and stable threshold voltage. But oxide vacancy control remains key to reliable device integration with BEOL metallization and CMP processes.

3D in FEOL, BEOL, packaging
Monolithic 3D integration describes the process of building two or more device layers “in place,” on a single piece of silicon. This use of 3D contrasts with 3D packaging concepts, which combine several finished chips in a single package, using layer transfer techniques in which device layers are fabricated separately and then combined. Several different approaches fall under the “monolithic” umbrella, though, depending on the requirements of the specific device. Monolithic integration also does not preclude the use of different substrates under the transferred layer.

CFETs, for example, stack silicon or SiGe-based PMOS and NMOS device layers in the FEOL, before any interconnect metallization takes place. Layer transfer is commonly used to combine different layers in CFETs. CFETs reduce the footprint of a pair of complementary transistors, increasing the overall transistor density.

However, 3D integration also can be used to shrink the distance between related parts of the circuit, reducing resistance of interconnecting paths and increasing overall speed. For example, in-memory computation modules, often proposed as a solution to the memory bandwidth bottleneck, might be placed directly above the primary CPU logic. RF devices do not themselves require aggressive scaling, but can still benefit from the shorter circuit paths that 3D integration can provide.

Within these in-memory compute and RF integration applications, the devices are part of the BEOL process flow and therefore face stringent thermal constraints. To prevent copper diffusion, process temperatures cannot exceed 400°C. Carbon nanotubes and 2D semiconductors have been proposed by researchers, but those technologies are still relatively immature.

Indium oxide semiconductors, however, are relatively mature and extensively used in display applications today. These indium oxide semiconductors may include tin (Sn), gallium, and/or zinc dopants. These layers are typically deposited by sputtering (physical vapor deposition) because the process readily achieve the low process temperatures required.

Moving ITO from displays to chips
Indium tin oxide (ITO) is perhaps the most mature indium-based semiconductor, with decades of manufacturing history in the display industry. In work presented at the recent VLSI Technology Symposium, Yuye Kang and colleagues at the National University of Singapore investigated the relationship between device figures of merit and channel thickness. They sputtered ITO onto prepared substrates with a tungsten back gate and hafnium oxide gate dielectric.[1] Using a 3.5 nm ITO channel with raised ITO source and drain electrodes, they appeared to stabilize the effective carrier mobility at 72 cm2/V-sec.

Though this carrier mobility is low by silicon standards, 72 cm2/V-sec is significantly better than values reported for previous ITO devices. Further reducing the channel thickness to 2 nm improved the subthreshold swing and threshold voltage, but device mobility deteriorated.

Fig. 1: Test structure demonstrating conformal ALD of IGO, ITO and HfO2 that potentially passivates oxygen vacancies while enabling deeper structures than sputtering. Source: 2023 VLSI Symposium [2]

Fig. 1: Test structure demonstrating conformal ALD of IGO, ITO and HfO2 that potentially passivates oxygen vacancies while enabling deeper structures than sputtering. Source: 2023 VLSI Symposium [2]

Interface scattering is known to degrade mobility in very thin semiconductor channels, including in silicon. In indium-based oxides, oxygen vacancies can also cause both mobility degradation and threshold voltage instability. Kaito Hikake and colleagues at the University of Tokyo, working with indium gallium oxide (IGO), suggested that ambient oxygen can also diffuse into the channel, creating deep traps.[2] Control of oxygen content and passivation of oxygen-related defects is a fundamental challenge for these materials, and researchers are taking a few different approaches. A separate National University of Singapore group, in work presented by Sonu (Devi) Hooda, used an ITO/IGZO (indium gallium zinc oxide) heterostructure.[3] In their work, the ITO thickness controlled the channel carrier concentration, compensating for oxygen defects. Meanwhile the heterostructure avoids the SS degradation and threshold voltage shift seen in ITO alone. Effective mobility, at 110 cm2/V-sec, was both superior to other results and importantly, independent of channel thickness.

Indium oxide, with and without gallium
Kaito Hikake’s group focused on the In-Ga portion of the In-Ga-Zn ternary phase diagram. Pure indium oxide achieves higher mobility; pure gallium oxide allows a larger band gap. In between the two, indium gallium oxide (IGO) maximizes thermal stability. While IGO is therefore very interesting theoretically, there have been few previous reports of practical devices.

The University of Tokyo researchers determined that In3Ga2Ox offered the best tradeoff between mobility, threshold voltage, and stability. While deposition by sputtering is possible, the researchers were specifically interested in vertical column FET structures and chose ALD for its conformality and excellent thickness and composition control. By alternating the GaOx and InOx sub-cycles, they defined the film composition. Next, they repeating this ALD heterostructure deposition as many times as necessary to produce the desired overall thickness.

The researchers fabricated both single and dual gate devices, with ITO gate electrodes and hafnium oxide gate dielectrics. Dual-gate devices achieved better drive current and mobility than single-gate devices, apparently due to passivation of the channel by the top dielectric layer. Specifically, ALD HfO2 grown using an ozone (O3) source stabilized the drain current and mobility without shifting the threshold voltage. Other passivation processes, including sputtered SiO2 and ALD of HfO2 with an H2O oxygen source, led to strong negative threshold voltage shifts.

Finally, Zhuocheng Zhang and colleagues at Purdue University observed that gallium does help to stabilize these devices, but still degrades electrical performance relative to pure In2O3.[4] They blamed the threshold voltage instability in indium oxide on the generation of oxygen vacancies under gate bias stress, the vacancies act as shallow donors. O2 annealing can passivate these potential donor sites, they suggested, without introducing the negative effects of Zn or Ga doping.

Practicality and BEOL devices
None of the devices discussed here are competitive with leading edge CMOS. They are, however, in the same neighborhood as amorphous silicon (αSi) and other semiconductors that can use low temperature processes. Regardless of the specific material, though, it is clear that oxide semiconductors based on indium are extremely sensitive to oxygen concentration, both during fabrication and in use. Proper encapsulation of practical devices will be essential to protect them during wet cleaning, CMP, and other process steps that might follow transistor fabrication and BEOL steps. It remains to be seen whether the flexible compositions of these materials will be an advantage, giving process engineers many ways to optimize devices for their specific needs, or a fundamental obstacle to consistent, reliable behavior.


  1. Kang, et. al., “Thickness-Engineered Extremely-thin Channel High Performance ITO TFTs with Raised S/D Architecture: Record-Low RSD, Highest Moblity (Sub-4 nm TCH Regime), and High VTH Tunability,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185421.
  2. Hikake et al., “A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185234.
  3. Hooda, et. al., “Overcoming Negative nFET VTH by Defect-Compensated Low-Thermal Budget ITO-IGZO Hetero-Oxide Channel to Achieve Record Mobility and Enhancement-mode Operation,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185266.
  4. Zhang, et. al., “Ultrahigh Bias Stability of ALD In2O3 FETs Enabled by High Temperature O2 Annealing,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185292.

Related Reading
True 3D-IC Problems
Stacking logic requires solving some hidden issues; concerns about thermal dissipation may be the least of them.
True 3D Is Much Tougher Than 2.5D
While terms often are used interchangeably, they are very different technologies with different challenges.

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