2D Semiconductors Make Progress, But So Does Silicon

By Katherine Derbyshire - 30 Oct, 2024 - Comments: 1

Semiconductor industry researchers have been anticipating the need for better transistor channel materials to replace silicon for a long time, but silicon devices have continued to improve enough to postpone that change. Silicon continues to provide an unmatched combination of device performance, manufacturability, and cost effectiveness. In recent years, though, the “end of silicon” cha... » read more

Will CFETs Help The Industry Go Vertical?

By Katherine Derbyshire - 15 Jun, 2023 - Comments: 0

Device scaling is getting much harder at each new process node. Even defining what it means is becoming a challenge. In the past, gate length and metal pitch went down and device density went up. Today, this is much harder for several reasons: • Short channel effects limit gate-length scaling; • Parasitic effects limit device density, and • Metal resistance limits metal pitch. So r... » read more

The History Of CMOS

By Paul McLellan - 25 May, 2023 - Comments: 0

Since CMOS has been around for about 50 years, a comprehensive history would be a book. This blog focuses on what I consider the major transitions. NMOS Before CMOS, there was NMOS (also PMOS, but I have no direct experience with that). An NMOS gate consisted of a network of N-transistors between the output and Vss, and a resistor (actually a transistor with an implant) between the output and... » read more

Managing Parasitics For Transistor Performance

By Katherine Derbyshire - 30 Jan, 2017 - Comments: 3

The basic equations describing transistor behavior rely on parameters like channel doping, the capacitance of the gate oxide, and the resistance between the source and drain and the channel. And for most of the IC industry's history, these have been sufficient. “Parasitic” or “external” resistances and capacitances from structures outside the transistor have been small enough to discoun... » read more

Reliability After Planar Silicon

By Katherine Derbyshire - 29 Jul, 2015 - Comments: 2

Negative bias temperature instability (NBTI) poses a very serious reliability challenge for highly scaled planar silicon transistors, as previously discussed. However, the conventional planar silicon transistor appears to be nearing the end of its life for other reasons, too. The mobility of carriers in silicon limits switching speed even as it becomes more difficult to maintain sufficient elec... » read more

Drill Down: Embedded NVM Technology

By Ernest Worthman - 02 Apr, 2015 - Comments: 0

Many of the next-generation devices that will be seen on the IoT/E will have power, footprint, and electronic constraints as never before. Electronic flash memories (eFLASH), and their derivatives are seen as a realistic solution to many of these design constraints for small form factor and simple IoE devices. “NVM will be very important for the IoE from the perspective of saving power," ... » read more

Next Channel Materials?

By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Chipmakers are making a giant leap from planar transistors to [getkc id="185" kc_name="finFETs"]. Initially, [getentity id="22846" e_name="Intel"] moved into finFET production at 22nm and is now ramping up its second-generation finFETs at 14nm. And the other foundries will enter the finFET fray at 16nm/14nm. So what’s next? Chipmakers will likely extend the finFET architecture to both 10nm... » read more

Ion Implanter Market Heats Up

By Mark LaPedus - 14 Aug, 2014 - Comments: 0

The ion implanter market has been a stable, if not a sleepy, business. The last big event took place in 2011, when Applied Materials re-entered the ion implanter market by acquiring Varian, the world’s leading supplier of these tools. The acquisition gave Applied Materials a commanding 80% share of the implanter business, with the other players fighting for the crumbs. But after year... » read more

Many Stresses Impact TSVs

By Ann Mutschler - 20 Feb, 2014 - Comments: 0

Too much stress in humans is typically not beneficial, and the same goes for 3D-ICs with through-silicon vias (TSVs). Stress effects here come from the fact that copper, which is the conductor of choice for the TSVs, and silicon have different coefficients of thermal expansion. “If you can imagine that a via will be etched through the silicon, copper will be deposited inside and then t... » read more

It’s A Materials World

By Mark LaPedus - 15 Aug, 2013 - Comments: 0

By Mark LaPedus At a recent event, Intel’s fab materials guru described a nightmarish occurrence that nearly brought the chip giant to its knees. Tim Hendry, director of fab materials and vice president of the Technology and Manufacturing Group at Intel, said the company obtained a critical material from an undisclosed supplier. “This large sub-supplier, a very large chemical company, m... » read more

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tag: NMOS