Managing Parasitics For Transistor Performance

Capacitances that used to be insignificant are becoming critical factors at advanced nodes.


The basic equations describing transistor behavior rely on parameters like channel doping, the capacitance of the gate oxide, and the resistance between the source and drain and the channel. And for most of the IC industry’s history, these have been sufficient. “Parasitic” or “external” resistances and capacitances from structures outside the transistor have been small enough to discount.

This is no longer the case. Reza Arghavani, managing director of technology at Lam Research, explained in a short course at last month’s IEEE Electron Device Meeting that contact resistance, resistance in the near-transistor interconnect stack, capacitance between the gate and the source and drain — all of these and more have an increasingly significant role in transistor performance. Beginning with the 32nm node, he estimates that external resistance will overwhelm the silicon channel resistance characteristics.

Nor will the proposed introduction of germanium and other alternative semiconductors help. These materials require buffer layers, cap layers, and other structures that are likely to make the problem worse.

Contacts and Schottky barriers
The increasing importance of parasitics is a direct result of transistor scaling. For example, source and drain contacts have long used silicide as an interfacial layer between the contact metal and the semiconductor. With very shallow, highly doped source and drain regions, even the small amount of silicon consumed by the silicidation process, can be too much.

However, silicides were chosen in the first place because direct metal-to-semiconductor contacts develop a highly resistive Schottky barrier, with the rectifying behavior of a diode rather than the simple ohmic resistance of a wire. This barrier alone can cause a 32% reduction in NMOS drive current relative to ideal silicon finFET behavior, Arghavani said. The barrier height depends on the offset between the Fermi level of the semiconductor — which is often pinned by surface states, independent of doping — and the conduction band of the metal at the interface. (Or the valence band for p-type semiconductors.)

Because the Schottky barrier involves surface interactions between the metal and semiconductor, it is very sensitive to surface preparation and can be minimized by the introduction of a suitable interfacial layer. Such a layer would, ideally, prevent electrical interaction between the two materials, be non-reactive with the metal, and offer a high dielectric constant with a low resistance to tunneling. This last characteristic introduces a tradeoff, as a low tunneling barrier necessarily allows more interaction between the semiconductor and the metal, increasing the Schottky barrier height. Researchers at Lam have had promising results from the insertion of a thin TiO2 layer between the silicon and the Ti/TiN contact liner.

Another approach, proposed by Gluschenkov and colleagues at IBM Research and GlobalFoundries (2016 IEDM paper 17.2), takes advantage of the observation that Ti on n-type Si has a relatively low Schottky barrier height. These researchers were able to achieve low resistivity contacts on highly P-doped Si with the help of laser annealing and solid phase epitaxy. Gas phase epitaxy plus a shallow implant created a localized mix of Si:P in a nanoscale contact trench. Laser annealing was used to induce epitaxial regrowth of the Si:P layer, followed by a Ti/TiN liner and a W contact plug. A second laser annealing step after the metal plug formed a low resistance silicide.

What about germanium?
The introduction of germanium-rich and other alternative materials further increases the complexity of junction and contact resistance management. Germanium transistors, for example, might use a germanium-poor SiGe contact layer, or a highly doped silicon cap layer. InAs contact layers also appear promising, as Ti on InAs appears to offer a low Schottky barrier (IEDM paper 25.1). Unfortunately, as Imec’s Nadine Collaert explained, this simply moves the issue down to the InAs/Ge interface, where the band offset between the two materials adds substantial resistance. Above 50% germanium, SiGe transistors will increasingly require buffer layers and lattice matching, too. Particular above 70% Ge, the external resistances due to such structures are likely to erode the benefits that germanium offers.

Aside from the resistance of the contacts themselves, continued reduction of gate pitch while gate length scaling has stalled means that self-aligned contacts must fit into smaller areas. Any misalignment can cause erosion of the gate during the contact etch. Atomic layer etch — in which a single layer at a time is first reacted with the etchant, then removed — allows much tighter control over etch profiles. Lam Research reports a 2X selectivity improvement, and a dramatic reduction in corner loss for the same contact landing area.

There’s not much that can be done, though, about the distribution of dopants in the source and drain. As discussed in this article on transistor reliability, the distribution of dopants in small features follows Poisson statistics. With very few individual dopant atoms, the observed behavior reflects the locations of discrete particles rather than a uniform distribution. This can lead to random fluctuations in contact resistivity.

Managing near-via resistance
The local interconnects pose significant challenges too, Arghavani said. The copper Via0 layer, connecting the tungsten local interconnect (M0) to the copper interconnect stack, has the smallest dimensions in the copper stack. Current crowding in the via and the amount of space occupied by resistive barrier layers combine to account for as much as 80% of the local interconnect resistance.

Though the use of TaN/Co barrier/liner bilayers has been considered to facilitate copper deposition, TaN/Ta bilayers have less resistance. One proposed alternative, investigated by students at Penn State, cuts the number of barrier layers in half by using a dual damascene integration scheme for both the tungsten contact and M0 structure and the copper Via0 + M1 structure. (See Fig. 1.)

Via resistance
Fig. 1: Single and dual damascene local interconnects. Courtesy IEEE.

Alternatively, Lam-sponsored research at Tohoku University has investigated replacement of the conventional W contact plug with Co, with the cobalt forming a low-resistance silicide. This material offers reduced resistance, and a CoTi liner could be used between the cobalt and the copper via layer.

Low-k dielectrics come to the transistor
Reducing gate pitch also reduces the thickness of the gate spacer, which in turn increases the gate – source/drain overlap capacitance. Similar concerns in the interconnect stack led to the introduction of low-k dielectrics, and low-k dielectrics have been proposed for gate spacers, too.

Just as porous low-k dielectrics reduce interconnect capacitance, air spacers offer the lowest possible Ceff between the source/drain and the gate. They have been been demonstrated for memory, and K. Cheng and colleagues at IBM and GlobalFoundries demonstrated (IEDM paper 17.1) integration of air spacers into a finFET process flow with replacement metal gates and self-aligned contacts. First, the proposed scheme selectively removes sacrificial gate caps and low-k spacers. It’s critical that the RIE process not affect the gate or contact metal layers. Thus, the high aspect ratio of spacers requires high selectivity. Micro loading in thin spacers degrades the removal rate of the sacrificial spacers, but trying to increase the removal rate tends to result in erosion of the metal. Careful optimization of the etch process was required.

After gap formation, the IBM group created spacers by first depositing a thin dielectric liner on the exposed sidewalls, then using a non-conformal dielectric to pinch off the gap. If the air gap spacer reaches the active fin, the high-k gate dielectric can be exposed, which can cause threshold voltage shift. Moreover, erosion of fins and source/drain contacts occurs. Using a liner and stopping the etch above the fin minimizes these risks. This group saw a 15% to 25% reduction in overlap capacitance and a 10% to 15% reduction in ring oscillator effective capacitance at 10 nm.

As transistor structures become more complex and use a wider array of materials, resistances at interfaces within these hetero-structures become more important. At the same time, smaller features both reduce the available process margin and force designers to pay attention to capacitances that were previously insignificant.

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MD says:

Very good article.

Amitava Chatterjee says:

Thank you for writing this article. Your simple writing style helps clarify what appears as a confusing and complex array of structures, integration schemes, and terminology used in describing the processing steps in what is called middle-end-of-line (MOL). Your figure 1 illustrates contacts to the source/drain and teaches what is meant by metal-zero. I have difficulty understanding the many process integration approaches used in this part of the fabrication process and would like to solicit your help in locating articles or blogs which teach in simple language and images. In particular, it is difficult visualizing three dimensional structures of FinFETs with contacts to the gate and the source/drain. Would there be two independent pattern of contacts? I believe you are implying that the dominant method used in production is single damascene for contact and M0 as well as for via0 and M1 (shown at the left side of Figure1). What prevents the use of dual damascene (also shown in Figure1) in manufacturing today? Moreover, there is mention of more than one level of metal-zero. Is that not an example of self-conflicting terminology? Shouldn’t the second one be called metal-one? Thank you again.

Katherine Derbyshire says:

Because these are new structures, the terminology is a little unsettled and can definitely be confusing. I think some of the confusion is because no one wants to put copper in contact with silicon. So, as the transistors get taller — FinFETs — the tungsten portion of the stack also grows. Different integration schemes handle the transition between tungsten and copper in different ways, with different terminology.

Dual damascene is quite commonly used in the upper layers of the metal stack. It is more challenging in the lower layers, as discussed here, because of the difficulty in filling very narrow, high aspect ratio features. The extra barrier layers also facilitate adhesion, also a challenge in such small features.

In the FinFET designs that I have seen, the gate wraps over the top of the fin, with the source and drain on either side of it. Seen from the top, it’s not that different from a planar transistor.

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