tag: atomic layer etch

Research Bits: July 11
By Jesse Allen - 11 Jul, 2022 - Comments: 0

Modeling ALE Scientists at U.S. Department of Energy’s (DOE) Princeton Plasma Physics Laboratory (PPPL), in coordination with Lam Research, modeled atomic layer etching (ALE) for semiconductor fabrication. “This would be one little piece in the whole process,” said David Graves, associate laboratory director for low-temperature plasma surface interactions at PPPL and a professor in th... » read more

Power Amp Wars Begin For 5G
By Mark LaPedus - 24 Aug, 2020 - Comments: 2

Demand is increasing for power amplifier chips and other RF devices for 5G base stations, setting the stage for a showdown among different companies and technologies. The power amplifier device is a key component that boosts the RF power signals in base stations. It's based on two competitive technologies, silicon-based LDMOS or RF gallium nitride (GaN). GaN, a III-V technology, outperforms ... » read more

Atomic Layer Etch Expands To New Markets
By Mark LaPedus - 16 Jul, 2020 - Comments: 0

The semiconductor industry is developing the next wave of applications for atomic layer etch (ALE), hoping to get a foothold in some new and emerging markets. ALE, a next-generation etch technology that removes materials at the atomic scale, is one of several tools used to process advanced devices in a fab. ALE moved into production for select applications around 2016, although the technolog... » read more

Manufacturing Bits: Feb. 18
By Mark LaPedus - 18 Feb, 2020 - Comments: 0

Molecular layer etch The U.S. Department of Energy’s Argonne National Laboratory has made new advances in the field of molecular layer etching or etch (MLE). MLE is related to atomic layer etch (ALE). Used in the semiconductor industry, ALE selectively removes targeted materials at the atomic scale without damaging other parts of the structure. ALE is related to atomic layer deposition... » read more

Cryogenic Etch Re-Emerges
By Mark LaPedus - 20 Sep, 2018 - Comments: 0

After years in R&D, a technology called cryogenic etch is re-emerging as a possible option for production as the industry faces new challenges in memory and logic. Cryogenic etch removes materials in devices with high aspect ratios at cold temperatures, although it has always been a challenging process. Cryogenic etch is difficult to control and it requires specialized cryogenic gases in... » read more

Where Is Selective Deposition?
By Mark LaPedus - 25 Jun, 2018 - Comments: 4

For years, the industry has been working on an advanced technology called area-selective deposition for chip production at 5nm and beyond. Area-selective deposition, an advanced self-aligned patterning technique, is still in R&D amid a slew of challenges with the technology. But the more advanced forms of technology are beginning to make some progress, possibly inching closer from the la... » read more

Big Trouble At 3nm
By Mark LaPedus - 21 Jun, 2018 - Comments: 0

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

Patterning Problems Pile Up
By Mark LaPedus - 20 Mar, 2017 - Comments: 4

Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

Managing Parasitics For Transistor Performance
By Katherine Derbyshire - 30 Jan, 2017 - Comments: 3

The basic equations describing transistor behavior rely on parameters like channel doping, the capacitance of the gate oxide, and the resistance between the source and drain and the channel. And for most of the IC industry's history, these have been sufficient. “Parasitic” or “external” resistances and capacitances from structures outside the transistor have been small enough to discoun... » read more

Etching Technology Advances
By Jeff Dorsch - 15 Dec, 2016 - Comments: 0

Let’s get really, really small. That directive from leading semiconductor companies and their customers is forcing the whole semiconductor supply chain to come up with new ways to design and manufacture ever-shrinking dimensions for chips. The current push is to 10nm and 7nm, but R&D into 5nm and 3nm is already underway. To put this in perspective, there are roughly two silicon atom... » read more

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