tag: cobalt

How To Compare Chips
By Ed Sperling - 15 Sep, 2022 - Comments: 0

Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

Week In Review: Auto, Security, Pervasive Computing
By Linda Christensen - 02 Sep, 2022 - Comments: 0

The great EV ramp EV-related developments are everywhere. California’s move to ban sales of new internal-combustion vehicles by 2035, and the U.S. government’s sweeping embrace of clean-energy, are in lockstep with recent moves by the auto industry and related supply chains, as well as cutting-edge research. One of the big breakthroughs is the ability to charge an EV in 10 minutes witho... » read more

Battery Management Getting Competitive For EVs
By Ed Sperling - 07 Apr, 2022 - Comments: 0

The success or failure of future electric vehicles will depend on where and how those cars are used, as well as significant advances in battery materials, energy density, and some very complex battery management systems. Battery power needs to be balanced, stored for extended times, and delivered to wherever it is needed most in real time. This is a huge challenge, and nearly everything in a... » read more

Extending Copper Interconnects To 2nm
By Laura Peters - 17 Mar, 2022 - Comments: 0

Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

Slower Metal Bogs Down SoC Performance
By Bryon Moyer - 15 Oct, 2020 - Comments: 0

Metal interconnect delays are rising, offsetting some of the gains from faster transistors at each successive process node. Older architectures were born in a time when compute time was the limiter. But with interconnects increasingly viewed as the limiter on advanced nodes, there’s an opportunity to rethink how we build systems-on-chips (SoCs). ”Interconnect delay is a fundamental tr... » read more

Power/Performance Bits: Sept. 9
By Jesse Allen - 09 Sep, 2020 - Comments: 0

Smaller, cheaper integrated photonics Researchers from the University of California Santa Barbara, California Institute of Technology (Caltech), and Ecole Polytechnique Fédérale de Lausanne (EPFL) developed a way to integrate an optical frequency comb on a silicon photonic chip. Optical frequency combs are collections of equally spaced frequencies of laser light (so called because when pl... » read more

Big Changes In Tiny Interconnects
By Ed Sperling - 16 Apr, 2020 - Comments: 1

One of the fundamental components of a semiconductor, the interconnect, is undergoing radical changes as chips scale below 7nm. Some of the most pronounced shifts are occurring at the lowest metal layers. As more and smaller transistors are packed onto a die, and as more data is processed and moved both on and off a chip or across a package, the materials used to make those interconnects, th... » read more

Unsticking Moore’s Law
By Ed Sperling - 04 Feb, 2019 - Comments: 2

Sanjay Natarajan, corporate vice president at Applied Materials with responsibility for transistor, interconnect and memory solutions, sat down with Semiconductor Engineering to talk about variation, Moore's Law, the impact of new materials such as cobalt, and different memory architectures and approaches. What follows are excerpts of that conversation. SE: Reliability is becoming more of an... » read more

Keeping Up Power And Performance With Cobalt
By Mehul Naik - 24 Jan, 2019 - Comments: 0

Chip designers require simultaneous improvements in “PPAC”: power, performance and area/cost (Fig. 1). Achieving these improvements is becoming increasingly difficult as classic Moore's Law scaling slows. What's needed is a new playbook for the industry consisting of new materials, new architectures, new 3D structures within the chip, new methods to shrink feature geometries, and advanced p... » read more

5 Observations From Intel’s Event
By Mark LaPedus - 17 Dec, 2018 - Comments: 0

Not long ago, Intel hosted its “Architecture Day,” where top executives from the chip giant revealed the company’s latest products and next-generation technologies. The company also discussed its strategy. To be sure, it’s a critical time for Intel. In June, Brian Krzanich was forced out as chief executive and the company is still looking for a permanent CEO. Plus, Intel has delayed it... » read more

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