5 Observations From Intel’s Event

Mysterious locations, codenames and process delays are on the top of the list.


Not long ago, Intel hosted its “Architecture Day,” where top executives from the chip giant revealed the company’s latest products and next-generation technologies.

The company also discussed its strategy. To be sure, it’s a critical time for Intel. In June, Brian Krzanich was forced out as chief executive and the company is still looking for a permanent CEO. Plus, Intel has delayed its 10nm process twice, putting it in an unfamiliar territory of playing from behind in the process race with Samsung and TSMC.

So, we need to know what’s next at Intel. At the event, Intel discussed a multitude of technologies. It demonstrated a range of 10nm-based systems in development. One of the big stars of the event involved IC packaging. Here are my five observations from the event:

1) The Da Vinci Code and Architecture Day
The event itself was a bit mysterious. I was supposed to drive from my home to a hotel somewhere in San Jose, Calif. There, other reporters and I were transported to an offsite location.

That location was shrouded in secrecy and Intel would did not tell us the exact place. As it turns out, we were transported to Los Altos at the former residence of Robert Noyce, the co-founder of Intel and co-inventor of the integrated circuit. (Noyce founded Intel in 1968 and passed away in 1990.)

The location was amazing. It is a distinctive estate compound on 4.55 acres. It also turns out that the current owner has the estate up for sale. The asking price–$21.8 million.

Meanwhile, at the event, Intel executives discussed its strategy in various segments—microprocessors, graphics chips, memory, etc. As with all products on Intel’s roadmap, the company uses an assortment of code names. For example, Intel introduced its next-generation CPU microarchitecture, dubbed “Sunny Cove.”

Then, Intel tossed out multiple code names at the event. It’s a bit perplexing to put all the names in place. I’m no symbologist, but after a while, I was able to decipher some of the codes.

Nonetheless, it was a good and informative event. Several sites, including AnandTech and Tom’s Hardware, provided comprehensive coverage of the event.

2) Where is 10nm (7nm and 5nm)?
In 2016, Intel announced its 10nm process with plans to ship a processor based on the technology in the second half of 2017. Intel is ramping up 10nm in high volume within two fabs—Fab 20 in Kiryat Gat, Israel and Fab 32 in Chandler, Ariz.

Today, though, 10nm is still not shipping in volumes. Intel has delayed the process twice and now plans to ship products based on 10nm in the second half of 2019. Some 10nm server devices won’t ship until early 2020. So at best, Intel’s 10nm technology is at least two years late. Some say it’s five years late.

Regardless, after holding a substantial lead in process technology, Intel is finding itself playing catch-up in the process race to two rivals. TSMC and Samsung are ramping up 7nm, which is equivalent to Intel’s 10nm. It’s more than that. For example, rival AMD, which is using TSMC’s 7nm process for its processors and graphics chips, is back in the game and presents a threat to Intel. There are other examples as well.

Still to be seen, however, is if Intel can ship 10nm under its new timeline. There are still no guarantees. But if it misses another window, then what? In R&D, Intel is working on 7nm and 5nm. But based on the traditional cadence, Intel should have released 7nm by now. So, 7nm and 5nm will be late.

I’ve asked dozens of people why Intel’s 10nm is late. Most are unsure. Some think Intel tried too much at once like cobalt interconnects for the lower levels and contact over active gate

I wouldn’t count out Intel just yet. They have the resources, know-how and technology to stage a comeback.

3) Changing its tune
Intel has been developing IC packages for years. For example, Intel has offered a silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB), which makes use of a tiny piece of silicon with routing layers that connects one chip to another in an IC package.

EMIB is a lower cost alternative to an interposer used in 2.5D packages, according to Intel, which has often dissed interposers as a viable technology.

At the event, Intel demonstrated a new 3D packaging technology, called “Foveros,” which enables logic-on-logic integration. Foveros enables 2.5D/3D packages and helps pave the way towards the chiplets model.

Even more interesting is that Foveros makes use of an active interposer, meaning Intel is changing its tune about the technology. Maybe interposers aren’t so bad after all and lends itself better to the chiplets model. EMIB is an interesting technology, but perhaps bridges in general are limited and difficult to implement for mainstream apps.

4) What about memory?
For some time, Intel has been developing two types of memory technologies—3D NAND and 3D XPoint. 3D NAND is the successor to today’s NAND flash, while 3D XPoint is a next-generation memory based on phase-change technology.

For both, Intel’s memory partner is Micron. But Intel’s commitment to memory has been thrown into question, when Intel and Micron recently announced plans that they would go their separate ways for both 3D NAND and 3D XPoint. Intel and Micron will finish the next designs for both technologies and will develop products separately.

Then, the other shoe dropped. 3D XPoint is made at Intel-Micron Flash Technologies (IMFT), a joint venture fab in Lehi, Utah. But in October, Micron assumed ownership of IMFT, creating more speculation in the arena.

For now, though, Intel remains committed to memory. For example, Intel’s Fab 68 facility in China has been ramping up 3D NAND. Intel plans to double the capacity of the China fab by mid-2019, according to sources. Long term, Intel wants to ramp up 3D XPoint in Fab 68, according to sources.

What about 3D XPoint? In September, New Mexico Governor Susana Martinez announced that Intel is moving its 3D XPoint memory technology development to the company’s Fab 11X facility in Rio Rancho, N.M. The move creates over 100 jobs at Intel’s Rio Rancho site. Intel is starting a 3D XPoint production line in Fab 11X. They are implementing a copy-exact process in the fab, which is the same as the IMFT technology. They’ve even hired some IMFT engineers and managers, according to sources.

“Intel and Micron will end the 3D NAND joint development this year and they are turning into full competitors. They don’t want to share any data and they want to beat each other with technology and price,” according to one source. “It will be the same next year for XPoint. They also want to tailor the XPoint process for different applications.”

5) What would Bob Noyce say now?
I wonder what Bob Noyce would say if he were at the event. I am guessing he would marvel with the innovations in the industry—the realization of AI and machine learning; self-driving cars; mobile devices and others.

He would also wonder about Intel’s footing. The company is still searching for a CEO. It’s playing from behind in some but not all markets. Worse, over the years, Intel has tried to expand beyond its core microprocessor business. Most of those efforts have flopped. The list includes ASICs, communication ICs, branded PCs, fault tolerant computers, security software, supercomputers and wearables.

It’s also no secret that Intel missed the initial cell phone wave, but it hopes to regain some lost time with a design win at Apple. 5G might happen at Intel.

Here’s what Noyce would really wonder about. Intel is late with 10nm and the former execs would do everything in their power to solve the issues overnight. Here’s what one Intel observer said: “I’m sure you’ve heard the same, but 10nm will ramp in 2019– finally. I’m still amazed that they don’t seem too excited about the 10nm slip.”

Not sure that would happen on Noyce’s or Andy Grove’s watch. Surely not with Gordon Moore. Like I said, don’t count Intel out. They have an impressive team of execs, R&Ders and marketeers. Let’s see if they can execute in 2019.

Leave a Reply

(Note: This name will be displayed publicly)