Deeper Inside Intel

Top process execs shed light on 10nm and beyond, plans for longer time between nodes, and the future of EUV, finFETs and stacked die.


Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those conversations.

SE: Intel recently announced its 10nm finFET technology. Can you describe the process?

Bohr: Regarding some of those process details, we’ll keep them close to our vest a little while longer. We did disclose some relevant data, the first of which is gate pitch. It’s a very key factor in scaling for both logic and memory. We showed another metric of gate pitch times logic cell height. So we disclosed enough to make the point that our 10nm technology is a big step forward, better than the usual 0.56x area scaling.

SE: Generally, the industry is taking longer to develop these new processes due to the complexity and other factors, right?

Bohr: Yes, it will take a little bit longer than our past trend of a two-year cadence. But it’s going to deliver a much better area scaling than before. As a result of some of these technologies taking a little bit longer, we are also planning ahead to make them more broadly available and extend their life by doing some more regular performance enhancements. For example, we will have 10nm, 10nm plus and 10nm plus plus. We will develop derivative technologies for the wider range of products that we are supporting.

SE: What’s different between Intel’s 14nm and 10nm finFET processes?

Bohr: There are always a few changes, but it’s too early to disclose exactly what those changes are. For gate pitch, we’re scaling about 0.76x per generation. But the other design rules are scaling at a faster rate. The result in that area, certainly on 10nm, is much better than the traditional 0.56x area scaling.

SE: When will Intel ship 10nm products?

Bohr: The second half of next year is our plan for volume shipments of our lead 10nm product.

SE: I assume Intel will offer 10nm for foundry customers, right? What other processes will Intel’s foundry business offer?

Ball: Very simply, we offer 22nm, 14nm and 10nm today.

SE: There is some confusion regarding the node designations. It started with 16nm versus 14nm. And the confusion will likely continue between 10nm and 7nm. Any comments?

Ball: The names of the nodes don’t exactly correlate with the features and capabilities. This is one of the fundamental confusing factors out there.

Bohr: It’s fair to say that Intel has pretty much continued our scaling trend, and a little bit better than normal on 10nm. Other companies in our industry appear to have a far less consistent technology scaling strategy. They were doing well up through the 28nm generation, and then there was a delay in getting finFETs out. As a result, they are now using aggressive sounding node names, like 14nm and 10nm. But if you compare the density of those technologies to their past trends, it’s quite clear that they are off that traditional scaling trend. As a result, they are behind Intel almost by a full generation in area scaling.

SE: Some foundry vendors will soon ship 10nm finFET processes. Are they ahead or behind Intel?

Bohr: Not all 10nm generations are the same. Others claim they are beginning to ramp their 10nm technology. It’s not the same as our 10nm. It’s almost a full generation behind. Of course, it’s more than two years ago that we ramped up our 14nm, which is more similar to their 10nm. But it’s a little bit hard to compare, at least on this point based on statements.

SE: Intel also developed a range of different interconnect stacks at 10nm, much like what you did at 14nm. Interconnect scaling is also challenging, right?

Bohr: Interconnect scaling is not as simple or direct as maybe transistor scaling. A tighter pitch interconnect comes with both good and bad news. The good news is that it provides better density, but the bad news is the performance and the RC delay will be degraded. And wafer costs may be higher, if you have more process and masking steps to enable that tighter pitch. It’s much more of a complicated tradeoff in choosing an interconnect stack and tuning it either for low cost, high density or high performance. You not only look at the tight pitch layers, but what combination of medium and looser pitch layers you will use to deliver the best results.

SE: How is Intel dealing with the complexity of the interconnects and other patterning steps?

Bohr: One key innovation that Intel introduced at the 14nm generation, and also scaling and improving upon it at 10nm, is the use of self-aligned double patterning. This is in contrast to the litho-etch-litho-etch that other companies have used. It not only serves us well at 14nm, but it will again on 10nm. Now, I believe other companies have also come around to that line of thought as well.

SE: So Intel is extending 193nm immersion and self-aligned double patterning at 10nm, right?

Bohr: That’s correct. Again, that’s part of the reason we chose it at 14nm. We saw that it would be a more scalable approach.

SE: So that means you will continue to use 1D layouts?

Bohr: Self-aligned double patterning tends to use more uni-directional wires, as opposed to the older style of bi-directional. Although you may want to have bi-directional, it’s sometimes just too expensive in terms of process steps and designs.

SE: What are the trends in power consumption?

Bohr: You may have noted it in one of the graphs that I showed in a recent presentation. It showed three trends over the past five generations of Intel technology. I showed the gate delay trend, the switching energy trend and then the product of the two. One important goal of scaling and Moore’s Law is to improve that energy delay. Of course, when you make dimensions smaller they tend to have lower capacitance per transistor or function. So, that’s where the energy benefit comes from. That’s something we pay close attention to when we scale technology. We make sure we’re scaling the capacitance per transistor or capacitance per function. So you get that switch energy benefit.

SE: What else?

Bohr: My graph also indicated that recent trends show maybe less aggressive gate delay improvement and more aggressive switching energy improvement. That’s an indication of increasing importance of lower power and lower power density in the technologies that we develop.

SE: Intel had some past issues with 14nm, forcing it to push out its 14nm process. What did you learn from that experience that you can apply to 10nm?

Bohr: On the top of my head, I can list three. One, we pioneered the use of self-aligned double patterning on 14nm with the knowledge that it’s scalable. The other issue is cycle time through the fab. Every technology generation gets more complex. We have to add more masking steps and other process steps. And if the rate of movement in the fab is the same per step, it will take you longer to complete the flow. We recognized that we didn’t do quite as well on that metric. That’s wafer movement per day in the fab on 14nm. So we’ve been much more aggressive the past two or three years and increased that pace of experimental lots moving through the development fab. And now we’re about 1.6x faster on our 10nm line than we were at a similar timeframe on 14nm.

SE: What else did you learn?

Bohr: On 14nm, we started with a full test chip with all of the metal layers. It just took longer to learn to optimize the transistors. On 10nm, we started with some simpler test chips. We still exercised all of the tight design rules, but this allowed us to make quicker progress on transistors and not have to wait for all of the backend steps to be done.

SE: Intel’s process cadence has moved from two years to 2.5 years. What about 10nm?

Bohr: I am not sure we are going to be quoting any expected cadence. 10nm may take a little bit longer. Maybe a better phrase is that each generation will be a little bit different.

SE: Some say 10nm will be a half-node and not necessarily a big node.

Bohr: Maybe for others. Not for us.

SE: Let’s talk about 7nm. Will Intel insert extreme ultraviolet (EUV) lithography for 7nm?

Bohr: We are developing our 7nm technology to be compatible with either all immersion or EUV at selected layers. Obviously, we would rather use EUV if it could deliver the manufacturability goals in terms of the uptime and wafers per hour. The EUV tools today are not at that point, so it would be risky to commit a technology to EUV. And it would just delay us if we had to hold off on developing 7nm to wait for EUV tools. Obviously, if we had EUV, we could do it with fewer masks, and thus, a lower total wafer cost.

SE: Can you do 7nm without EUV?

Bohr: We are well down the path of developing our 7nm technology today on an all-immersion process. We are closely monitoring the health progress of EUV tools. But again, they are not yet at that maturity level that we could say we’ll be committing them for 7nm.

SE: Does Intel plan to extend the finFET to 7nm and/or 5nm? Or will you move to another transistor type?

Bohr: Exactly what options and features will be chosen for 7nm or 5nm is something I won’t comment on.

SE: But the finFET still has a lot of life, right?

Bohr: We have to recognize that finFET transistors are pretty darn good for leading a range of product requirements, from high performance and low leakage. That’s a pretty tough set of requirements to supplant with another technology. But that’s happened. High-k/metal-gate replaced polysilicon Sio2. And tri-gate replaced planar. So eventually, silicon tri-gate will be replaced too.

SE: The finFET is an option for 5nm. So is gate-all-around. Beyond that, there are vertical nanowires and others. Any thoughts?

Bohr: They are all great ideas in a PowerPoint, but it’s a little bit tougher to put them in silicon in high-volume manufacturing. Gate-all-around is certainly a logical extension to finFETs. FinFETs provide an electrostatic improvement over planar devices, and gate-all-around may provide the next improvement in electrostatics. But you have to add up all of the transistor parameters to make sure they deliver high performance. You need good electrostatics, high drive current, low capacitance, good density and very wide performance verses leakage and dynamic range.

SE: What about cost?

Bohr: Obviously, we look for new ideas and new technologies that provide the biggest bang for the buck. You might have a transistor or interconnect idea that provides better performance or density. But maybe the cost is too high. That’s a factor, but not the deciding factor.

SE: In a recent paper, Intel benchmarked various channel materials, such as germanium and III-V, for a gate-all-around device. Are those materials ready today?

Bohr: They are still immature. The point of that paper is that we have maybe two different scaling vectors. One vector is that you want to improve the electrostatics, maybe by going to finFETs or gate-all-around. The other vector is that you change the channel materials from silicon to germanium or III-V to have better mobility. The point of the paper is that we have to ask ourselves: ‘Are there some combinations that are better and some that are worse?’ Maybe you want to go to gate-all-around, but maybe you still stay with silicon. Or maybe you want to go to a III-V channel, but it has to stay with a finFET-type structure. We just can’t make a decision on one of those vectors and one those options. We have to look at what combinations make the most sense.

SE: Let’s switch to the foundry business. What is Intel’s foundry strategy?

Ball: If I had to put it in a nutshell, I’d say the strategy is taking it one step at a time. We have great technology, but then we have to bring IP, the ecosystem, services and a business lens to all of those things. We try to be a bit selective about where and what markets we go after. Some time ago, we started out with the network infrastructure segment like FPGAs and network processors and those kinds of customers.

SE: What’s changed?

Ball: The second area focus for us is mobile. The challenge there has been you need to have a significant ecosystem of partners and IP to enter that segment. We believe we’ve put that together.

SE: Intel also announced an IP deal with ARM. What does that bring to the party?

Ball: With ARM joining Intel’s ecosystem, that puts us in position to support any mobile business. This makes it easier for the customer to adopt an ARM solution on Intel technology.

SE: Intel competes at the high-end of the foundry business with finFET processes at 22nm, 14nm, and now 10nm. Yet, there are many companies that are still at the trailing edge. What about those customers?

Ball: We are probably not going to go back to 45nm and put a lot of investment in that. Over time, our 22nm platform may become attractive to customers that are more at the trailing edge. As people look to move forward from 28nm today, they may look at Intel for 22nm and 14nm as an option. There are also people on 40nm today that are still thinking about going to 28nm or 22nm and when. So, we’ll keep 22nm and 14nm alive. And we’ll continue to invest in the ecosystem for those.

SE: What about FD-SOI?

Bohr: The short answer is that I really don’t think FD-SOI provides any significant advantage over scaled bulk finFETs. I still believe finFETs will be a better solution for density, performance and power.

Ball: FinFETs have an advantage for low leakage and IoT applications.

SE: Fewer and fewer foundry customers can afford to move to the next node due to costs. Any thoughts?

Ball: On the leading node, there is not a huge list of companies. And companies pick their partners carefully. Customers are looking for particular things. And so our goal is to line up a solution for a given customer.

SE: Intel has leading-edge technology, but it takes more than that to succeed in the foundry business, right?

Ball: It’s a service industry. If we were just selling technology, it would truly be easy. There is a lot of trust required. If you are a fabless semiconductor company, your foundry is the lifeblood of your business. If they let you down, you go nowhere. So, it’s important that you have the right level of service.

SE: Let’s discuss packaging. The industry has been developing 2.5D products using interposers and TSVs. Intel has taken a different approach with a technology called Embedded Multi-die Interconnect Bridge (EMIB). Any comments?

Bohr: In both cases, whether it’s EMIB or an interposer in 2.5D, the goal is to be able to connect multiple chips together with a low cost and a dense substrate. But the real key advantage of EMIB is that it requires only tiny pieces of silicon at the die boarders to connect together the silicon in the package. Compare this to an interposer in 2.5D. You’ve got one huge piece of silicon, which is much more expensive. Not only is it a big piece of silicon, but then you need expensive through-silicon vias to get the signals from top of the interposer down into the package.

SE: What kinds of chips can you use with EMIB?

Bohr: With Embedded Bridge, a 14nm or a 10nm logic die can connect directly to the package. The technology can work for combining a variety of other chips. It can be two different 14nm logic chips. It could be a 14nm logic chip, next to a 22nm eDRAM chip.

Ball: High bandwidth memory is an interesting case. This is where EMIB really shines. You can avoid the cost and complexity of the silicon interposer. EMIB is a flexible platform. When you combine it with our sort and test technology, that lets you manage the yields of the various different die. It’s a capability to build products quickly at a reasonable cost.

SE: You recently talked about Intel’s R&D budget for packaging. Can you elaborate?

Ball: Our assembly and test R&D is larger than the top two OSATs combined. Packaging is something we’ve done for a long time. If you look across Intel’s product line, you’ll see lots of innovative packaging.

SE: Customers also have the option of using third-party OSATs, right?

Ball: We don’t put any artificial constraints on the business. Typically, once customers see what our assembly and test capabilities are, that tends to be a highlight of the collaboration.

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To 7nm And Beyond
What Transistors Will Look Like At 5nm
One-On-One: Mark Bohr


memister says:

0.56x area scaling with 0.76x gate pitch scaling means the interconnect pitch goes from 52 nm to 38 nm. But he says better than that so it’s <38 nm pitch. So I'm gonna guess 37 nm minimum interconnect pitch.

Carlos Lemos says:

Hope to see at least 30% single thread improvements on flagship arm cores by 2H 2017.

Dolan1998 says:

You dont have to wait so long. 😉

In Q1 2017 we will have here phones with new A73 architecture clocked at around 3 GHz.

Btw. I dont expect Intel made 10nm devices anytime soon, not even 2H 2017. We even dont know, if he mean delivering of enginering samples or final silicons. (in foundry world you want to tape-out your product at least year before release)

Remember Altera failure? First they told that 14nm FPGAs will be on market in 2013. Reality is, that 3 years after and they still did not release them.

Why redactor did not ask about this?

memister says:

No mention of SAQP but specifically SADP. Does it mean they did not use SAQP?

Sang Kim says:

Sang Kim
The major differences between 7nm and 5nm are as following: 7nm has a fin structure while 5nm has a rectangular structure. Lets take a close look at 5nm transistor. At 5nm node we have a 5nm at the bottom and 5nm at the topmost as well indicating a rectangular shape, not fin shaped, thus not finFET any more. Therefore, finFET ends at 7nm and not beyond. That is the end of 5nm node. Lets look some other issues with 5nm.
For planer devices when hot carriers are generated, electrons go to the positively biased drain and holes go to the substrate with no harm. Suppose the holes go to the source instead. Then the transistor can’t function. These phenomena occur in all nana tubes including horizontal as well as vertical including GAA(gate all around) device. That is why nana tubs are not manufactured today and will not be. This is because all holes go to the source instead of going to the substrate. This is because nanotube devices don’t have the substrate.
Furthermore, how can you suppress the leakage current due to the short effects at 5nm? or the punch-through for such un-doped 5nm channel? The leakage current due to such short channel effects will end 5nm. Also, even if 5nm could happen, 5nm wouldn’t outperform 7nm! Then why 5nm should be manufactured?

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