One-On-One: Mark Bohr

Intel’s process guru on taller, thinner fins; cheap interposer alternatives; and new materials and technologies on the near and distant horizon.


Semiconductor Engineering sat down to discuss process technology, transistor trends, chip-packaging and other topics with Mark Bohr, a senior fellow and director of process architecture and integration at Intel.

SE: Intel recently introduced chips based on its new 14nm process. Can you briefly describe the 14nm process?

Bohr: It’s our second-generation, tri-gate technology. So it has all of the features of the first generation and more. It has thin silicon fins, but we made them thinner and taller. We packed them closer together. It still has hafnium-based high-k dielectrics and metal gate electrodes, but they are just smaller.

SE: At 22nm, Intel’s finFET technology had a fin pitch of 60nm and a fin height of 34nm. At 14nm, the fin pitch and height are both 42nm. What do thinner and taller fins bring to the party?

Bohr: That improves the electrostatics of the fins. So the gate has better control over the flow of current through the channel. It turns on and off better. Maybe more importantly, it has better performance at low voltage, partly because it has lower variability. The improved variability allows us to operate our circuits at lower voltage. Of course, lower voltage means lower active power.

SE: In Intel’s tri-gate technology, there has been much talk about the shape of the fins. What’s that about?

Bohr: We had all sorts of comments about our trapezoid-shaped fins at 22nm. They were not perfectly rectangular. And for the 22nm era, that worked for us. We knew how to do that in high volumes. In fact, we’ve shipped 500 million of those chips. But we knew back then that ideally we wanted tall and skinny fins. With that first-generation tri-gate experience behind us, we learned how to do these further improvements at 14nm, including learning how to make the fin tall and skinny.

SE: How far is Intel ahead of the competition in finFET technology?

Bohr: You never know until our competitors ship. In 2015, we will see other companies ship tri-gate or finFET transistors. Then, we’ll see what they exactly offer in terms of the dimensions, features and performance capabilities. In the meantime, some companies are just beginning to ship their 20nm planar products. So again, we’re shipping our second-generation tri-gate technology, while many are working to ship their first-generation.

SE: Didn’t Intel experience some yield and defect issues with the 14nm process?

Bohr: There was no one showstopper. It wasn’t like we didn’t know how to do the fins or we couldn’t do the tight interconnects. It was just a variety of issues. Some were random. Some were systematic. Some were related to the transistors. Some were related to the interconnects. Because the features are so small and advanced, it was difficult to learn how to solve those problems. But we did that. It took us a little bit longer than what we would have liked.

SE: What type of patterning technology are you using at 14nm and what about extreme ultraviolet (EUV) lithography?

Bohr: We are using 193nm immersion, spacer-based lithography for our 14nm technology. That looks to be scalable to 10nm. So we don’t have to use, or wait, for EUV to do our 10nm technology. Right now, I am working with a team of engineers exploring options for our 7nm technology. Even more so, we would like to have EUV for 7nm, but I can’t really count on that. So we are also exploring the option of a non-EUV version of 7nm. It looks doable. At this very early stage, we can achieve better density and lower cost. But if I had EUV, I could do a much better job. So we are still looking at and exploring EUV for 7nm, but we are not absolutely counting on it for 7nm.

SE: Can you extend 193nm immersion and multiple patterning down to 3nm? By then or sooner, will the industry require octuple patterning?

Bohr: Maybe from an academic point of view, you can do that. You can just keep adding masks. And theoretically, you can achieve very small feature sizes. But two things will limit you here. The number one problem is cost. There are so many layers. You can achieve these small features, but it will cost you so much and you have not achieved a lower cost per transistor. There are other things that will limit you. You will have so many resist steps required to form one layer. When you get to the next layer, which one do you align to? So you have an alignment sequence that you have to worry about. Those layers could be misaligned relative to each other and these alignment tolerances add up, especially when you talk about 7nm technology.

SE: What about interconnects and RC delay in scaling?

Bohr: Unlike the transistor, the interconnects tend to get slower. You can address that with more hierarchical interconnects. And, of course, we are looking at new materials and ultra low-k dielectrics.

SE: At 7nm, the industry may need to use III-V materials in the channels to boost mobility. In general, what’s the status of III-V technology?

Bohr: Germanium is clearly the leading candidate for the p channel in the device. N channel is a tougher problem. You might have to look at more exotic III-V materials. But changing the channel materials is a big increase in the complexity, not only because it will likely have to be different between p and n, but you may have to change the material in the silicon substrate. Then, you have to worry about how you get this new material on silicon. And you have to worry about making transistors for a very wide span of applications, from high performance to very low leakage. So III-V channels must not only provide high performance capabilities but also very low leakage. At very low leakage, you are limited by band-to-band tunneling. Sub-threshold leakage may be more of a problem with some III-V materials. So developing a universal, or widely useful, transistor from high performance to very low leakage is quite a challenging task.

SE: Some say the III-V materials have been pushed out or delayed. Any thoughts on that?

Bohr: Other companies may choose to push out the adoption of III-V, because all of the problems have not been solved for the 10nm generation. Tool readiness doesn’t seem to be the issue. It’s mostly device physics.

SE: At 7nm, the industry may need to go to a new transistor structure. The options include III-V finFETs, gate-all-around FETs, quantum well finFETs and SOI finFETs. Has Intel made a decision about its next-generation transistor technology yet?

Bohr: Our research group has cast a wide net in terms of what transistor options, materials and structures would be best for 7nm. We have not made that decision yet. Answering that question becomes an ever more complex problem. You not only want to make it smaller, and provide better performance, but it also has to have low capacitance and low leakage. It’s a tall set of requirements.

SE: Some believe that gate-all-around is the frontrunner in the industry at 7nm. Any comments?

Bohr: That wouldn’t surprise me greatly. I won’t comment beyond that in terms of what Intel sees as the favorite.

SE: For years, Intel has dismissed SOI. Have you changed your stance about SOI?

Bohr: We still have the same open mind as we’ve had for many years. We’ve looked at SOI, but bulk continues to provide the performance features we want at a slightly lower cost. Maybe someday, or at some generation, that will change. But it hasn’t yet.

SE: Intel recently announced an advanced packaging technology called Embedded Multi-die Interconnect Bridge (EMIB). What is that?

Bohr: We’ve thought about the packaging problem for a while. Silicon interposer is one of the solutions. You can get tight interconnects to connect two or more silicon chips, but it’s expensive. So what we announced is something we call embedded bridge. It has many of the good features of the silicon interposer, but not the cost. It’s a very small bridge, just between the two chips you want to connect together. So that small piece of silicon is embedded in the packaged substrate. You can still get the very dense bandwidth connections between the chips, but without the significant cost of a true silicon interposer.

SE: Does this mean that Intel has dismissed the idea of doing advanced stack die with TSVs?

Bohr: No. We have a very active TSV program. This is becoming applicable in the low-power handheld product space, where you want dense bandwidth between memories stacked on top of a logic chip.

SE: For some time, the industry has been talking about the so-called post-CMOS era, possibly beyond 3nm. There are a number of futuristic technologies on the table, such as carbon nanotubes, graphene, TFETs, spintronics and others. Any thoughts?

Bohr: Our research group has screened some of these options. This will not only help Intel, but it will help the university research groups identify the more promising options that we should collectively invest in. It may change as more researchers weigh in, but the conclusion at this point is that spintronics may have a better chance in the future.


Dr.Mefityiszto says:

“post-CMOS” moved to 3 nm? That’s funny how that’s get postponed, like EUV. 🙂 Go CMOS!

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