Transistor Options Beyond 3nm

Despite a slowdown in chip scaling amid soaring costs, the industry continues to search for a new transistor type 5 to 10 years out—particularly for the 2nm and 1nm nodes. Specifically, the industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, accord... » read more

New Nodes, Materials, Memories

Ellie Yieh, vice president and general manager of Advanced Product Technology Development at [getentity id="22817" e_name="Applied Materials"], and head of the company's Maydan Technology Center, sat down with Semiconductor Engineering to talk about challenges, changes and solutions at advanced nodes and with new applications. What follows are excerpts of that conversation. SE: How far can w... » read more

Silicon’s Long Game

The era of all-silicon substrates and copper wires may be coming to an end. Progress in the future increasingly depends on more exotic combinations of materials that are developed for specific applications. But after years of predicting the death of silicon, it appears those predictions may be premature. That's not always obvious, given the growing number of chemical combinations being creat... » read more

Light In A Package

Silicon photonics is gaining significant traction inside the data center, but creating a simpler method of packaging the laser with other circuitry remains a stumbling block for cutting costs and using this technology across a wider swath of applications. Progress does appear to be on the horizon, even though exact time frames remain unclear. The advantages of light in communications are wel... » read more

Integrated Photonics

Semiconductor Engineering sat down to discuss the status of integrated photonics with Twan Korthorst, CEO for PhoeniX Software; Gilles Lamant, distinguished engineer for [getentity id="22032" e_name="Cadence"]; Bill De Vries, director of marketing for Lumerical Solutions; and Brett Attaway, director of EPDA solutions at AIM Photonics, SUNY Polytechnic Institute. What follows are excerpts of tha... » read more

Ruthenium Liners Give Way To Ruthenium Lines

For several years now, integrated circuit manufacturers have been investigating alternative barrier layer materials for copper interconnects. As interconnect dimensions shrink, the barrier accounts for an increasing fraction of the total line volume. As previously reported, both cobalt and ruthenium have drawn substantial interest because they can serve as both barrier and seed layers, minimizi... » read more

What’s After FinFETs?

Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it's still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next. The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process ... » read more

Foundries Accelerate Auto Efforts

Foundries are ramping up their efforts in automotive chip production in preparation for a surge in semiconductors used in assisted and autonomous driving. All of the major foundry vendors are scrambling to assemble the pieces and expand their process portfolios for automotive customers. The foundries are seeing a growing demand from automotive IC customers amid the push toward advanced drive... » read more

What’s Next In Scaling, Stacking

An Steegen, executive vice president of semiconductor technology and systems at [getentity id="22217" e_name="Imec"], sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies... » read more

TFETs Cut Sub-Threshold Swing

One of the main obstacles to continued transistor scaling is power consumption. As gate length decreases, the sub-threshold swing (SS) — the gate voltage required to change the drain current by one order of magnitude — increases. As Qin Zhang, Wei Zhao, and Alan Seabaugh of Notre Dame explained in 2006, SS faces a theoretical minimum of 60 mV/decade at room temperature in conventional MO... » read more

← Older posts