tag: silicon interposers

TSV Complexity Leads To Manufacturing Bottleneck
By Laura Peters - 22 Apr, 2026 - Comments: 1

Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

Thermal-Mechanical Optimization of 2.5D Flip-Chip Packages With Glass and Silicon Interposers (Univ. of Ottawa)
By Technical Paper Link - 06 Jan, 2026 - Comments: 0

A new technical paper titled "Thermo-mechanical co-design of 2.5D flip-chip packages with silicon and glass interposers via finite element analysis and machine learning" was published by researchers at University of Ottawa. Abstract "Advanced 2.5D flip-chip packages with silicon/glass interposers may pose tightly coupled thermo-mechanical trade-offs. This work presents a simulation-driven, ... » read more

When To Move To Multi-Die Assemblies
By Ann Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

Advanced Packaging Driving New Collaboration Across Supply Chain
By Gregory Haley - 24 Oct, 2024 - Comments: 0

The semiconductor industry is undergoing a profound shift in packaging technologies to ones that rely on close collaboration among multiple stakeholders to solve intricate, multi-faceted, and extraordinarily complex problems. At the heart of this change is the convergence of heterogeneous integration, chiplets, and 3D stacking. Heterogeneous approaches allow companies to combine different te... » read more

Chiplets: Current Status
By Andy Heinig - 12 May, 2022 - Comments: 0

Recent weeks have seen a number of interesting developments in the area of chiplets. An increasing number of products based on chiplets have been brought to market, especially in the processors segment. For example, Apple and AMD now have processors with chiplets on the market and under production in high volumes. On one hand, this means that sufficient production capacity has now been built up... » read more

Heterogeneous Integration Using Organic Interposer Technology
By Amkor - 17 Nov, 2021 - Comments: 0

As the costs of advanced node silicon have risen sharply with the 7 and 5-nanometer nodes, advanced packaging is coming to a crossroad where it is no longer fiscally prudent to pack all desired functionality into a single die. While single-die packages will still be around, the high-end market is shifting towards multiple-die packages to reduce overall costs and improve functionality. This shif... » read more

Fan-Out And Packaging Challenges
By Mark LaPedus - 06 Oct, 2021 - Comments: 2

Semiconductor Engineering sat down to discuss various IC packaging technologies, wafer-level and panel-level approaches, and the need for new materials with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of globa... » read more

Interconnects Emerge As Key Concern For Performance
By Ed Sperling - 03 Sep, 2020 - Comments: 0

Interconnects are becoming increasingly challenging to design, implement and test as the amount of data skyrockets and the ability to move that data through denser arrays of compute elements and memories becomes more difficult. The idea of an interconnect is rather simple, but ask two people what constitutes an interconnect and you're likely to get very different answers. Interconnects are e... » read more

What’s After PAM-4?
By Bryon Moyer - 23 Jun, 2020 - Comments: 1

[This is part 2 of a 2-part series. Part 1 can be found here.] The future of high-speed physical signaling is uncertain. While PAM-4 remains one of the key standards today, there is widespread debate about whether PAM-8 will succeed it. This has an impact on everything from where the next bottlenecks are likely to emerge and the best approaches to solving them, to how chips, systems and p... » read more

Making Silicon Photonics Chips More Reliable
By Ed Sperling - 09 Jun, 2020 - Comments: 0

Silicon photonics has the ability to dramatically improve on-die and chip-to-chip communication within a package at extremely low power, but ensuring that signal integrity remains consistent over time isn't so simple. While this technology has been used commercially for at least the past decade, it never has achieved mainstream status. That's mostly due to the fact that Moore's Law scaling h... » read more

← Older posts

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy