Making Silicon Photonics Chips More Reliable

More data and new applications are making this technology increasingly attractive, but it’s still not mainstream.


Silicon photonics has the ability to dramatically improve on-die and chip-to-chip communication within a package at extremely low power, but ensuring that signal integrity remains consistent over time isn’t so simple.

While this technology has been used commercially for at least the past decade, it never has achieved mainstream status. That’s mostly due to the fact that Moore’s Law scaling has met the bulk of power/performance needs at a price point well below silicon photonics. As a result, silicon photonics has been limited to applications such as networking chips, where price is less of a factor and latency and low power are critical. But as the benefits of Moore’s Law dwindle, and as more data needs to be processed and moved around more quickly — particularly in growing markets such as automotive LiDAR — silicon photonics is attracting much more interest. Along with that, there is a strong focus on how to add consistency and reliability across all applications of this technology.

“There are four classic markets for photonics,” said Tom Daspit, product manager at Mentor, a Siemens Business. “One is sensors, which are typically very small designs. The second is networking outside the box, where you have Ethernet on one side and fiber on the other. We’re also seeing some companies doing photonics with an interposer, while others are using a die on a substrate. The third is LiDAR, and the fourth is network switching. We’re also seeing a whole bunch of startups doing quantum computing, and some are using photonics to drive Josephson junctions.”

One of the new areas being explored is chip-to-chip communication within a package, and communication between modules within a device. The main approach that has been used so far relies on a silicon interposer, where through-silicon vias act as waveguides for optical signals.

“Your typical signal is going through a converter, and then a transceiver, and then to optical cabling,” said Calvin Cheung, vice president of engineering at ASE. “What you want to do is reduce the size of the interconnect between the ASIC and the optical transceiver. When you want to get such a high speed, copper cannot handle it. The [redistribution layer] on silicon cannot handle it. It’s better to do that with a waveguide on a silicon interposer, where you create a trench that acts as a waveguide. Shrinking the interconnect improves the signal integrity and power efficiency. If you’re driving through copper, you’re wasting a lot of energy.”

Pushing this into the mainstream isn’t so simple, however. For one thing, the cost of silicon photonics needs to come down, which will require both more standard processes and much wider adoption. It also requires innovations on a number of levels, from design all the way through to test and inspection.

There also are multiple issues that can crop up with photonics chips that affect reliability. Among them:

  • Warpage. Photonics requires different materials than electrical circuits, so the photonics chip — typically a III-V material — needs to be bonded to the silicon. Because they have different coefficients of thermal expansion, that can put stress on the solder balls or bumps and cause warpage, which can skew the optical signals.
  • Drift. As with analog circuitry, optical circuits are affected by aging, heat, and various types of noise. That can cause variation in signals, which may push them outside the range of the optical filters that receive them.
  • Waveguide roughness. Waveguides need to be perfectly smooth in order not to disrupt optical signals. Any aberrations, which are the equivalent of line-edge roughness in digital chips, can impact signal integrity. In addition, optical circuits must be either linear or relaxed curvilinear to the signals to keep flowing smoothly, which isn’t a focus of design tools today.
  • Variation. While most of the manufacturing for silicon photonics chips is done at older nodes, this is still a relatively new manufacturing process. The light-emitting lasers themselves use III-V materials that need to be bonded somehow to silicon, and packaging of these types of chips is still being perfected.

All of these issues and others will need to be addressed.

Materials and physics
“Silicon photonics wafers typically incorporate both logical and optical components on the same wafers,” said Mike Slessor, CEO of FormFactor. “These optical components, such as lasers, waveguides, detectors and multiplexers can interface directly with the classic logic components, or can be combined as separate ICs through advanced 2.5D and 3D advanced packaging techniques. Therefore, the new dimension in silicon photonics wafer test is a hybrid of electrical and optical measurements.”

Silicon photonics is different than the optical communications inside a data center today. While light has been used to carry large amounts of data over varying distances, those distances typically have been quite large. Moving it much closer to the processing by incorporating it into a chip or multi-chip package adds a whole new level of complexity.

Materials pose another problem. Sufficient supply and purity of materials is critical. The most popular include gallium arseninde, indisum arsenide, indium gallium arsenide and indium phosphide. These III-V materials are essential in silicon photonics because of their direct bandgap, but they are difficult to work with, degrade over time — which is why most photonics applications include redundant lasers — and they never have been produced in mass quantity. Silicon, in contrast, is extremely stable but a poor emitter of light due to its indirect bandgap.

There are other materials in this mix, as well. For example, transition metal dichalcogenides are used to maintain the amplitude and power of the optical signals, which are deposited in the form of thin films. But while all of this is relatively straightforward for manufacturing, all of these are exotic materials.

On the plus side, most of these chips are not being developed at leading-edge nodes. As with analog, shrinking features doesn’t help.

“Silicon photonics chips are being produced at 45nm or 65nm nodes, and in some cases on much smaller substrates,” said FormFactor’s Slessor. “I know a few people have done 300mm, but a lot of what’s being done is on smaller substrates, leveraging an installed base of semiconductor production equipment, is pretty cost-effective. The dimensions and the material sets you’re dealing with are relatively simple. It’s pretty amenable to the trailing edge installed base of fab capacity.”

Packaging everything together makes this much more complex, however. “The bigger problem in working with these materials is structural”, said Raanan Gewirtzman, chief business officer at proteanTecs. “The reliability hit comes from a few different directions. With advanced packaging, you need to find ways to put these dies together and make sure you address issues of heat. So you may use TSV or microbumps to connect different dies, and when you have a lot of dies in the same package you have to deal with massive connectivity. It has now become necessary to monitor the interconnects and signal quality to make sure the whole system is functioning properly.”

As with all chips, particularly high-performance digital or mixed-signal chips, heat is an issue. The benefit of silicon photonics is that it doesn’t produce much. The drawback is that heat from other sources can cause optical signal drift. Optical filters need to be recalibrated to account for that drift in order to avoid signal loss.

Design constraints and differences
Designing photonics chips is very different than electrical. Crossing circuits in optical is not a violation and does not cause shorts as it does with an electrical design. In addition, most of the photonics chips have been developed at 130nm and 90nm, although some are beginning to ramp 65nm, which makes them less expensive and easier to work with.

The bigger problem is the lack of tooling, which has made designing digital and even analog/mixed signal chips much more consistent over the years.

“You have to be an expert in custom layout,” said Mentor’s Daspit. “There are no standards, and there is no prevalent methodology today. If you’re putting this into a package, you have to get one or more fibers through the package. The challenge is how you get the light on and off the chip. If you’re using grating couplers, they come in on an angle. If you’re using an edge coupler, it comes in at the same plane as the die. But either way, you have 2D/3D alignment issues.”

That will require some changes, which in the past were viewed as unnecessary because of the niche role that silicon photonics played. But in higher-frequency communication such as 5G and potentially automotive applications, silicon photonics suddenly is looking much more interesting than in the past. But utilizing this technology will require much more consistency in the design through manufacturing process.

“There’s going to be specialized silicon or other fabrication processes for dealing with specialized needs, whether it’s to do with very high frequency radio waves with silicon germanium or gallium arsenide, or whether it’s specific processes to deal with photonics,” said João Geada, chief technologist at Ansys. “Sure, you can integrate some of it with normal conventional CMOS, but it’s easier when it isn’t. And you don’t need the very high cost of an extreme node when the features you put on it are to manipulate light, which is actually much larger than the smallest transistors you make.”

Another challenge is determining how far light can be bent before it causes problems. That needs to be built into floor-planning and packaging tools. “You can only bend light so tight,” said Daspit. “You also may need to use structures that will delay light because networking applications run at fixed frequencies.”

Coverage and reliability issues
Analytics and test add other challenges, particularly when it comes to coverage.

“Silicon photonics is hard to analyze,” said Doug Elder, vice president and general manager at OptimalPlus. “You’ve got a mix of data types and you have to do something with those. You get some benefit if you can massage that data in a format that you can do something with, but historically these have been different silos.”

The key there is creating a semantic layer and adding predictive models, Elder said. “What you’re looking for is feedback that is timely so that the time to volume is condensed.”

Testing, meanwhile, tends to follow the same approaches as with conventional chips, only more complex.

“Most of the test methodologies we’re developing are analogous to the way people do electrical test today,” Slessor said. “So if you look at our overall system, it’s got a variety of lasers and detectors that are driving optical signals through the silicon photonics chip while electrically modulating things to turn structures on and off or change wavelengths a little bit. And then you’re measuring the output, as well. So you got a set a lasers, a set of detectors, and a set of electrical inputs and outputs that are measuring a variety of different things. If it’s a modulator, you’re trying to measure things associated with the switching, the overall figure of merit associated with the device. So it really is pretty analogous to what we do in mainstream electrical test. It’s just that now you now have this optical component, as well.”

Still, this is not a cookie-cutter approach. “Different customers have taken different approaches,” Slessor said. “Some of them have done fully homegrown bench solutions. I’m not sure I’d call it production test. It’s more like characterization and engineering test. You can get away with things that aren’t as efficient, high-throughput and well-integrated as today’s mainstream CMOS testing. But we’ve worked with a variety of customers, including GlobalFoundries and ITRI, and partners like Keysight, to integrate a complete test system primarily for wafer-level silicon photonics. It’s an area where, as people start to ramp in production, we’re seeing more and more demand for that integrated system. Even though we’re still at small volumes, it allows them to ramp quickly They don’t have to worry about integrating different test instrumentation with different handling hardware. Of course, you’re looking at measurements that are not just optical, but electrical, as well. And so it’s one of these hybrid applications where being able to integrate everything together in a turnkey way helps time to results and time to market for our customers.”

Silicon photonics is already a proven mix of technologies. It is expected to become more important over time as the amount of data that needs to be moved quickly continues to increase, and as more volume leads to better tooling and lower prices.

The fact that most of this development can happen at pre-finFET nodes is a big bonus, particularly when lower power, lower heat and higher performance are factored in. But consistency, reliability and better tooling still are required to push this into the mainstream, and at this point there is a lot of work left to do.

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