Return Of The Organic Interposer

Lower-cost options gain attention as chipmakers seek alternatives for 2.5D packaging.


Organic interposers are resurfacing as an option in advanced packaging, several years after they were first proposed as a means of reducing costs in 2.5D multi-die configurations.

There are several reasons why there is a renewed interest in this technology:

  • More companies are pushing up against the limits of Moore’s Law, where the cost of continuing to shrinking features is exorbitant.
  • Enough work has been done with organic interposers on the manufacturing side to deal with some of the main issues, such as warpage and difficulty in attaching other die to that interposer due to its flexibility.
  • There has been progress made to increase the density of organic interposers so they are closing in on silicon interposers.

Until now, most of the implementations of 2.5D have been for high-speed networking and server applications because the cost of a silicon interposer is so high. That price tag averages about $30, according to industry sources, but it can be as high as $100 when multiple reticles need to be stitched together, which puts it well out of the reach of many applications. And that’s just the start. A yield issue with multiple chips running through that interposer can ratchet up the cost of a respin or field failure even higher.

This helps explain why foundries have kept this technology on a very tight leash, and why there has been so much experimentation with alternatives to silicon interposers, including both organic materials and glass. So far, neither has made a huge dent in the market, but there is certainly a lot more attention being focused on them recently. The question is whether they ultimately will replace silicon interposers based on cost, whether they will be used for different lower-performance applications, or whether they will be relegated to a small niche.

“There was a push for 2-2 line/space in organic interposers” said Philippe Gastaldo, CTO at UnitySC. “That has been difficult. But there has been a big improvement recently at Japanese companies. They are getting closer.”

Not everything requires a 2-2 line/space, however. “Organic interposers are okay today for low-cost products,” said Andy Heinig, a research engineer in Fraunhofer’s Engineering of Adaptive Systems Division. “There is a compromise. You need multiple good chips, and conductivity for organic is not as good as silicon. But it is cheaper. And for automotive work, it’s easier than silicon and it’s smaller than fan-outs. To get camera data from a car you need to place cameras all around the car. That sounds easy, but you can quickly run into space limitations. It’s not the same limit as you might find in a mobile phone, but it’s still a problem. A silicon interposer will give you higher performance in a small space, but an organic interposer is only going to cost $2 to $3.”

Not so fast
Still, not everyone believes organic interposers ultimately will play a major role in semiconductor packaging. For one thing, there are plenty of alternatives available, including high-end fan-outs, bridges such as Intel’s embedded multi-die interconnect bridge (EMIB), system-in-package, and even planar FD-SOI. Advanced packaging has evolved from an interesting future technology to a crowded market filled with lots of options, each adding their own tradeoffs.

“Silicon and organic are two different ways to solve the same problem,” said Ingu Yin Chang, senior vice president at Advanced Semiconductor Engineering (ASE). “Silicon is shown to work in high-performance computing. But fan-out is more cost effective, and you can use the same tools already in use for the same line and space. You also can extend a 300mm wafer to a 600 x 600 panel. So if you compare the two, fan-out uses a chip substrate, the same equipment, it has a lower cost, and you don’t have to deal with a CT (coefficient of thermal expansion) mismatch.”

Chang said it is possible to create high-density organic interposers, but questions whether it will still be cost-effective once that density is reached. “Organic is in the middle between silicon interposers on one side and fan-outs on the other. The question is whether it will get squeezed out over time, and so far yield is highly questionable. At this point, no one is making a 2-2 line/space organic interposer that is in high production.”

Even if organic interposers do survive among all the different packaging options, the technology likely will take time to gain momentum.

“Organic interposers would need to have finer line width/line space to support the current design rules of 2.5D TSVs,” said Seung Wook Yoon, director of group technology strategy for the JCET Group. “This would be a challenge for yields in large panel sizes. One of the advantages of organic interposers was supposed to be lower cost. In order to achieve finer line width/line space, organic interposers may need a thin-film process, which would be an additional cost and it would require more time to establish the process. For example, laser direct imaging (LDI) was developed for printed circuit boards a long time ago, but it was not commercialized until demand for wafer-level packages began to increase.”

Focus turns to redistribution layer
While much of the focus in 2.xD packaging involves interposers, the real issue may be less about the material used in the interposer itself and more about what goes on in the redistribution layer.

A redistribution layer is used to re-route contact points to different layers, which in turn allows higher contact density. In effect, an RDL is a solution to a routing problem caused by extreme density in a fixed amount of space.

Fig. 1: Redistribution layer. Source: Lam Research

But the RDL increasingly is being looked at for much more than just floorplanning, and it brings along its own set of issues. The old method of back grinding proved far too destructive, so the industry has shifted to a carrier wafer that is coated with a releasable bonding material. This is complex materials science, because the materials have to be able to withstand multiple high-temperature steps and mechanical stress with no delamination or distortion.

There are two main approaches here. One is to create the RDL first, and then add the chips. The other is to create the chips, and then build up RDL around those chips.

Fig. 2: Different RDL approaches. Source: Renesas

“One of the problems is that you’re working with thermoplastic, which has to be combined with release layers, and if you need higher temperatures for manufacturing then you have to bond at higher temperstures,” said Rama Puligadda, executive director of advanced technologies at Brewer Science. “We’ve been working on bonding at a lower temperature with a curable layer on the carrier side. So one side is responsible for rigidity. The other is the bond.”

Brewer is experimenting with several new approaches that may have an impact on how all the pieces fit together. One uses a laser-ablation process to remove dielectric materials from the substrate, which works on feature sizes less than 5 microns. The advantages of this approach are that it can be processed at room temperature with precise depth and sidewall angle control. The challenges include figuring out a way to remove the ablated material, surface roughness, and the speed of this whole process.

The company also is working on using a thin film in a mold compound that can be stenciled for the chip. “This is not an interposer,” Puligadda noted. “It’s a replacement for EMC (epoxy mold compound). You pre-form a stencil where you want to make cavities in silicon.”

Fig. 3: Laminated polymetric die-stencil fill concept. Source: Brewer Science

Samsung is working on an RDL approach to packaging, as well, using an organic bridge that is bonded to the RDL. The company calls it a 2.5D RDL-Interposer. In a recent presentation to analysts, Dae Woo Kim, vice president at Samsung Electronics, said a mechanical sample was released in Q4 of last year. He said this also can be used for a fan-out system-in-package, where the die can be arranged side-by-side around the interposer.

This has generated a lot of buzz in the packaging industry. Samsung has been talking about organic interposers for the past couple years, terming packages based on these interposers 2.1D to distinguish them from silicon interposers in 2.5D. That also has prompted the IEEE to tighten up the nomenclature around 2.5D. There is an effort underway to group all types of organic interposers under 2DO, for both chip-first and chip-last organic-based connectors, and 2DS for passive silicon-based packages, with or without TSVs.

Fig. 4: 2DO vs. 2DS. Source: IEEE/Raja Swaminathan

“The details of Samsung’s organic interposer technology are not fully known, but such a solution may be possible because fine line width/line space patterns in a whole panel would indeed be a difficult challenge,” said JCET’s Yoon. “The JCET Group has a similar RDL bridge approach for high-density 2.1D or 2.5D devices. Ultra Fine-Pitch Organic Substrate (uFOS) achieves line width/line space requirements down to 2/2um and multiple redistribution layers (more than 10) in a thin, flexible structure. uFOS is a cost-effective alternative for 2.5D TSV technology, particularly when used in a 2.5D fan-out wafer-level packaging solution or 2.1D organic interposer.”

Shifting priorities
Initial ideas about the value of advanced packaging have shifted to the economic difference in different packaging approaches, rather than comparing advanced packaging to planar SoCs designed at the most advanced process nodes. This is a sign that advanced packaging is now a mainstream option for chip design and manufacturing.

But it’s a long way from the initial discussion about advanced packaging, which is that it allows chipmakers to choose IP based upon availability, price, and the thermal/electrical characteristics of that IP—regardless of the process node at which it was developed. This argument was always particularly attractive for analog IP, which doesn’t benefit from scaling, which is why analog IP used in SoCs at the advanced nodes is mostly digital.

“This is still about adding more functionality into a chip with a smaller die,” said Amin Shokrollahi, CEO of Kandou Bus. “You may want to put a SerDes right on top of bumps, but that creates a lot of heat, and you need a way to get the heat out. So the flexbility of die placement is really important because the spaces between these blocks have to be short. Organic substrates and interposers allow for some flexibility, but you need to be able to put SerDes directly on top of them, and that may not be possible. We talked to a lot of companies. Flexibility in placement and design is at the top of their list.”

Also becoming critical is a way of characterizing the different advanced packaging approaches so the industry can compare which of a long list of different possibilities is best for a particular application.

“We’re seeing this with silicon and glass interposers, and we’re seeing it with reconstituted wafers and mold compounds,” said Laura Rothman Mauer, chief technical officer at Veeco. “These are all organic. But the question is whether you can get the dimensions you need for a particular application. With packaging, there is definitely a need for flexibility, whether that’s 2D, 2.5D, 3D, fan-out wafer-level processing, and whether you’re doing etching or dry film or silicon wafer thinning and cleaning.”

Organic interposers remain one of many options on the table when it comes to packaging. They have distinct advantages in terms of cost, but they also are flexible. While that in itself can be a good thing, because they are less likely to crack under handling, multiple industry sources say that manufacturing processes need to be adapted to deal with them. So far, the jury is still out as to how widespread this approach will become because it will require enough volume to warrant those changes.

Samsung has been consistent in its statements about this approach. And while the industry dismissed FD-SOI for more than a decade as a niche technology, it seems to have found a solid market opportunity at 22nm, with 18nm and 12nm on the horizon from Samsung and GlobalFoundries and ST Microelectronics, respectively.

But there are so many choices available for packaging today that it’s difficult to make predictions about which will be successful in the long term, let alone figure out which approach to take for the next generation of a heterogeneous computing architecture. Organic interposers are still in the running, but so are a bunch of other options.

Related Stories
Advanced Packaging Confusion
Number of options and naming conventions are causing consternation throughout the semiconductor supply chain.
Cheaper Packaging Options Ahead
Low-cost alternatives to interposers could have a big impact on chip design.
Bridges Vs. Interposers
Momentum growing for low-cost alternatives to interposers as a way of reducing overall development costs.


Michael Mingliang Liu says:

It’s rather surprising to me that, with respect to @semiEngineering featuring an article on organic substrates and interposers, neither Rogers nor Kyocera was invited to the related discussions. I’d suggest, if I may, that the author compile a follow-up article (or, Part II), in order to include what either company would have to say about this particular subject matter. Thanks in advance.

Rogers has been supplying mature 2.5D organic “interposing” solutions to address RF/Microwave SiP challenges for years. So has Kyocera. Ask also Qorvo and MACOM for their MCM experiences…

masa says:

i do not think the technologies of rogers and kyocera are mature yet so that the authour did not include them.

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