Cheaper Packaging Options Ahead

Low-cost alternatives to interposers could have a big impact on chip design.


Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging.

By far, the most cited reason why companies don’t adopt advanced packaging is cost. Currently, silicon interposers add about $30 to the price of a medium-sized die, according to several industry sources. For large chips, where multiple reticles need to be stitched together, that price can increase to more than $100.

This has limited interposers to high-performance applications such as high-speed networking and server chips, where price is less of an issue. For those applications, 2.5D has proven to be a competitive necessity because it provides a significant boost in performance. An interposer can include thousands of through-silicon vias, which collectively provide fast signal throughput even though the individual TSVs are not as fast as other high-speed interconnects. In conjunction with that, different chips such as memory and logic can be placed closer together than blocks on a single chip, further enhancing performance and lessening the amount of energy required to drive signals.

But an interposer isn’t the only path forward, and silicon isn’t the only material under development. There are multiple types of interposers in research, including organic materials and glass, both of which are less expensive options. And there are scaled down bridges being developed at a fraction of the price of an interposer, although exactly how much these will cost isn’t clear. So far, only Intel has a commercially available bridge, and the company doesn’t break out that price separately.

Behind the scenes there is a frenzy of activity involving advanced packaging. This includes universities, chip companies such as Qualcomm, AMD and HiSilicon, foundries such as GlobalFoundries, TSMC, UMC and Samsung, and at all of the major OSATs. There is work happening throughout the semiconductor ecosystem, as well, from EDA tools to manufacturing equipment and test.

“There is overall agreement that silicon interposers are expensive, and that fan-outs can do everything that a silicon interposer can do,” said Ram Trichur, director of business development for Brewer Science’s Advanced Packaging Unit. “There is a lot of talk about Intel’s EMIB (Embedded Multi-Die Interconnect Bridge). There also are competing technologies being developed, including IME’s (A*Star’s Institute of Microelectronics) embedded fine-pitch interconnect and Samsung’s RDL (redistribution layer) bridge. All of those come at this from a lower-cost perspective.”

Along with that, it’s possible that fan-outs and other packaging approaches could replace the substrate, Trichur said. “You can’t do that with chip first, which was one of the initial approaches. But with RDL first, you build the RDL first, so you have a known-good RDL, and then known-good die on RDL.”

Fig. 1: RDL-first flow. Source: Brewer Science

What is becoming clear is that with advanced packaging, all options are on the table and more are being added. “The industry is very interested in EMIB and bridge in substrate,” said Seung Wook (S.W.) Yoon, director of product technology marketing at STATS ChipPAC. “But at this point you cannot fully replace TSVs because they’re the only option in the supply chain. Right now, EMIB is the only bridge that is commercial available, and Intel is the only one offering it.”

That will change as more interconnect options emerge from R&D.

“We are still in a phase with this technology where there is development of technology and purchasing of technology from suppliers that made the initial investment,” said Hugh Durdan, vice president of strategy and products at eSilicon. “We’re seeing two different approaches. One involves an interposer, or even an organic interposer. The second involves new innovative packaging technologies, where you get the density without the cost penalty. That includes EMIB, TSMC’s InFO, Shinko Electric’s approach, where you use a standard organic substrate with thin-film layers, and a silicon interposer with a finer pitch. But for large SoCs with HBM and a 55mm to 65mm package, there is no solution available today except silicon interposers. There are other solutions that are low-cost, medium density, which is what you see with InFO and RDL bridges. But for chips with HBM, the connections need to be very dense. With regular DRAM, you don’t need all of that density.”

Back to the future
One approach that is seeing a resurgence involves multi-chip modules, a packaging approach that has been around since the 1980s, when MCMs were used in mainframe computers. The advantage of an MCM is that it provides the same kind of flexibility as a PCB, but in a smaller form factor, and it provides a comparatively inexpensive platform for adding in high-speed interfaces.

The USR Alliance, started by Marvell and Kandou Bus, refers to MCMs as the new PCB, and it is developing an ecosystem of interoperable components. USR stands for ultra-short reach links, which typically are 2.5cm or less.

Fig. 2: Fully modular MCM-based SoC. Source: USR Alliance

Marvell, for its part, has been exploring a number of packaging options since it introduced its MoChi (modular chip) architecture in 2015. The initial idea behind MoChi was to pick IP from a menu of Marvell’s technology, which could then be packaged using Marvell’s interconnect. The company has since broadened that out with the USR Alliance, creating a 500 Gbit bi-directional interconnect that can be used to hook together any IP.

“We evaluated a number of packaging options and found that in order to make the technology common enough, the best solution is a standard organic substrate in an MCM package,” said Yaniv Kopelman, networking CTO for Marvell’s Connectivity, Storage and Infrastructure business unit. “All the OSATs know how to do it and there is no limit on the number of chips or placement of the die. This is the most compelling solution, and it’s cost-effective. Everything else is semi-proprietary. The initial thought was that MCMs would be bandwidth-density limited and that there would be huge overhead on power and area. We’ve found that to be less significant on big devices than we expected.”

He said silicon-proven MCMs use less than 0.8 picojoules per bit, which works out to roughly 400 milliwatts using a 500 Gbit bi-directional interconnect. “That’s six to seven times less power than SerDes, and it’s very robust. You can drive signals a very long distance-20 to 25mm within a package. And you can replace die whenever you want, because this is very flexible. There are other interfaces in various states, but this is readily available. You’re going to start to see more companies developing interfaces.”

MCMs and systems in package, which are sometimes described as vertical versions of MCMs, were generally overlooked in the race to put multiple die into a package because those technologies have been around for so many years and failed to live up to their initial promise. But they do add a level of flexibility to packaging, which is valuable in markets where companies want to get products out the door quickly or where specs or user demands change rapidly.

“Whenever we talk to customers about this, it’s always about speed and power,” said Mike Gianfagna, vice president of marketing at eSilicon. “Beyond that, it comes down to robustness and cost. But if you can get this to work in an MCM, that would be very interesting. Silicon interposers are delicate, which adds a yield and cost issue.”

MCMs come in different flavors, depending on whether they use ceramic or deposited metal substrate. Systems in package (SiP) were originally supposed to be vertical versions of MCMs, integrating separate die within a package, but the distinction between these two has been blurred over the years as companies introduced MCMs and called them SiPs for marketing reasons. Even some of the fan-out technology is very similar.

“Chip last, side-by-side, is no different than what we did for MCMs for many years,” said Calvin Cheung, vice president of business development and engineering at ASE. “And how you qualify those chips is no different than for any other process yield.”

New approaches
Even without the interposer, packaging isn’t as simple as initial proponents had suggested. There are costs and issues associated with advanced packaging that are not obvious to chipmakers when they first begin looking at this approach.

“For die-to-die connections, you may need to fan out,” said John Hunt, senior director of engineering at ASE. “EMIB may not give you that option because a die has to be designed for that. It’s hard to flip small bumps and large bumps. This is one of the reasons we’ve been focusing on a hybrid solution. You can flip a chip onto a regular BGA substrate, which takes the place of an interposer and it doesn’t need a one-micron line and space. And thermally it’s better because it’s thinner.”

There are other options that could help with this, as well. 3D multi-chip package-on-package is under development, which could help shave costs off putting everything on the same chip. This approach requires a redistribution layer on one side of a chip, through-package vias, and a redistribution layer on the other side.

“We’re seeing real interest in this approach,” said Brewer Science’s Trichur. “We’re also seeing a lot of innovation in RDL first.”

With RDL first, the RDL is built on a carrier wafer, which is usually glass. From there it is patterned multiple times times to build up the RDL. A mold compound is then added to create a 3D material. That can be repeated for as many layers of RDL as required. The problem with this approach is that it’s not quick. It may take two to three hours to cure each layer, Trichur said.

Once the curing is finished, a laser is used to separate the RDL from the glass. This has taken a lot of structural and materials engineering because if the RDL is too rigid it can create mismatches, and if it is too pliant it will not separate easily from the glass.

Why now?
Behind all of this work are several drivers. One is that the benefits of scaling to 7nm and 5nm are becoming harder to realize, and there are fewer companies that are benefiting from that scaling. Even Apple has begun combining the benefits of advanced packaging with the latest process node technology. But as the cost of developing chips continues to rise at each new node, and the potential unit volumes flatten or shrink, it’s becoming harder to justify integrating everything into the same die at the most advanced nodes.

Processors will continue to push to the next node for awhile, but even there wires have stopped scaling. Moreover, hardware increasingly is being defined by software, rather than software being developed to take advantage of generic hardware. Systems companies increasingly are using a variety of accelerators geared to specific data types, rather than generic hardware. Some of that data is analog in nature, and analog itself doesn’t scale.

“The push will continue for integration at smaller nodes,” said Navraj Nandra, senior director of marketing for the DesignWare Analog and MSIP Solutions Group at Synopsys. “But we’re also seeing short-channel effects, which cause leakage, starting to creep in again. That was under control with the first finFETs at 16/14nm. But the roadmap goes down to 4 or 3nm, or beyond, and at that point leakage begins creeping in, which is why you’re starting to hear about gate-all-around to control that leakage. That means integration will continue to happen, and we will still develop high-speed I/Os down to 3nm. But disintegration is happening, too. People are coming up with packaging options today, either side-by-side or stacked, which uses TSVs or interposers. Packaging may make it worthwhile to develop products you might not be able to develop without crazy high expenses. This is particularly true for deep neural networks, convolutional neural networks and machine learning—especially the inferencing side. Inferencing has to happen in real time in a car.”

Yield, test and other issues
As with all packaging, a key issue is yield. Packaging multiple good die together increases the cost of a failure by as many chips as there are in a package. So while the individual die are generally smaller, which improves yield of those die, a failure in any part of the package can affect all of the pieces.

“SiP modules use different form factors that depend on the IP from different manufacturers,” said Anil Bhalla, senior manager for marketing and sales at Astronics Test Systems. “But even if you have 100% test coverage of the different chips, the final product is not 100% coverage.”

This will be particularly important with panel-level packaging, which can offer huge economies of scale if yield is sufficient. But it also requires a number of changes in handling and materials, because like any package it is subject to stress and warpage, as well as a different approach to testing.

“With system-level test, whether it’s a panel or a module, you have higher confidence about whether a device is good or bad,” said Bhalla. “But how you handle a panel is a lot different than a SiP. This is still an emerging field.”

It’s one that will continue to gain traction, though, because all of these options offer benefits in terms of cost and time to market. But there is an increasing need to view this from a system-level perspective rather than a single die or even a wafer.

“When you find a problem, it’s a lot more expensive,” said ASE’s Cheung. “Even if you have all known good die, there are so many variables that can go wrong. With a system in package, assuming you have have known good die isn’t enough because every die may be operating at the corner of the spec, so all of the performance budget is eaten up. You need to produce known good die with enough margin. From an assembly point of view, you have vias, traces on the substrate and bumping, so there are multiple things involved, but they’re all grouped under connectivity. It’s hard to narrow where connectivity failed. And as you approach the edge of the wafer, it’s more sensitive to drift. The usual test area is in the center of the wafer, so you test in the center of the wafer, but the test pattern in the middle of the wafer is different than the rest of the wafer.”

Advanced packaging already has gone mainstream for some applications, but this is just the beginning. From here, the semiconductor industry will do what it does best—continually reduce costs and improve quality and predictability over time.

“Bridges, buffers and intermediate silicon are more available today than they were several years ago,” said Steven Woo, vice president of solutions marketing at Rambus. “The challenge is that these are all additional components, and you need to be able to extract value with those additional components.”

This will all take time, but given the proliferation of packaging in high-performance devices and the continued demand for more flexible approaches to building heterogeneous systems, momentum continues to build to make all of these different approaches work.

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