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Moore’s Law Now Requires Advanced Packaging


Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

Advanced Packaging Confusion


Advanced packaging is exploding in all directions. There are more chipmakers utilizing different packaging options, more options for the packages themselves, and a confusing array of descriptions and names being used for all of these. Several years ago, there were basically two options on the table, 3D-ICs and 2.5D. But as chipmakers began understanding the difficulty, cost and reduced benef... » read more

Cheaper Packaging Options Ahead


Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more