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Moore’s Law Now Requires Advanced Packaging

Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.


Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. What follows are excerpts of that conversation. Read part two and part three of this series.

L-R: Walter Ng, UMC; Calvin Cheung, ASE; Ajay Lalwani, eSilicon; Vic Kulkarni, ANSYS; Tien Shiah, Samsung. (Photo credit: Patricia MacLeod/ASE)

SE: Where do you see advanced packaging going, whether it’s 2.5D or fan-out or something else? And coinciding with that, what problems are beginning to surface?

Shiah: We’re looking at it from the HBM (high-bandwidth memory) side, and it’s fairly leading-edge. So one of the big challenges is the cost. You go into this area because it enables you to have the fastest type of DRAM memory to address very challenging problems in AI and machine learning. People need to use this type of memory to get the fastest training times.

Cheung: Advanced packaging is sorely needed for a number of applications. At 7nm, CMOS scaling becomes too expensive. The development cost and the wafer cost become almost unbearable for most companies, so you need to put a solution together with different technologies. You use different chips from different foundries. Advanced packaging, and especially SiP, are playing a role there. The OSATs are helping the industry to lower those costs and continue CMOS scaling, but using SiP to advance it using much more effective and cost-compelling approaches. You’re looking at CMOS scaling and also system integration. If you go back 50 years, mainframe computers were as big as a room. Now, we have 1,000 times that capability in a smart phone. Without advanced packaging, there is no way the iPhone could shrink to the size it is today. In the future, packaging will be the central technology that will enable miniaturization with power efficiency. We are shrinking the interconnects to reduce power consumption and increase the power efficiency. Whether it’s Google or TSMC or UMC, the main goal is energy efficiency. Advanced packaging plays a critical role in that.

Ng: From an economic standpoint, how many companies can afford silicon at the bleeding edge nowadays? That number is shrinking. For the very, very high performance markets, there is always going to be that need. But in the supply chain, from a volume standpoint, the chasm is opening up in the middle. The very leading edge needs 7, 5 and maybe 3nm someday. But everyone else has slowed down quite a bit. You can look at the need for advanced packaging in multiple places. At the leading edge, it’s absolutely necessary for integration of very high-end ASICs and HBM. The original idea was heterogeneous integration. From an economic standpoint, you can take a 40nm die and maybe a 0.25 micron die and basically look at it as a chip rather than a board. Advanced packaging is, in my mind, hitting the economic border of what foundries can do in silicon. It also enables the very high end.

SE: It’s sort of a rebound effect, right? We’ve gone from board to chip, and from chip back to something closer to a board. The difference is that it’s now in the same package.

Ng: That’s right. It’s like the days when we looked at the data books from companies such as TI, Fairchild and National Semiconductor. Now we’ve moved from chips to chiplets and small die, and you’re integrating them with advanced packaging. I see a lot of this from very high-end customers and very cost-conscious customers. With 2.5D interposers, we see a lot of volume being driven by high-end graphics and high-end enterprise. But we also see a lot of interest from consumer and other potentially high-volume applications that require good performance, but maybe not bleeding-edge performance. They’re looking at it from whether they can get a more effective cost point.

Kulkarni: Our challenge is how we serve this transition from Moore’s Law to More Than Moore, where you’re not just pushing feature sizes. Data speed is a critical part of this. We see that extremely high-speed SerDes driving 5G, moving from 58G to 118G. With photonics we see people going from 200G to 400G. With ADAS in particular, the latency has to be minimal, and there is no way to do that unless you create extremely high-performance chips. And then, how do you solve all the issues between the chips? ADAS and 5G will drive 2.5D, and that will require improvements in interposers. Silicon interposers are now causing trouble with electrical loss and power noise and signal integrity. Corning’s CTO recently talked about glass interposers. The glass interposer has the highest resistivity and very low loss. Some of our end customers and the foundries are now talking about that in order to enable 5G, ADAS, AI, HBM2, and chiplets. That’s becoming the new paradigm of meeting extremely low latency rates and high performance.

Lalwani: From the system perspective and where systems are going, advanced packaging is central to that. We’re already hitting the limits of I/O in a system. We’re hitting the limits of power and electrical performance. When you combine those, it’s not enough to just keep going down the process geometry curve. It doesn’t solve all the other problems associated with 5G networks and AI. This is still scaling, but it’s happening in a different dimension. It’s not just process.

SE: 2.5D is a proven option for very high-speed and cost-insensitive designs, but it’s still a long way from the mainstream. What has to change to make it more affordable?

Ng: Everyone splinters onto different paths. That doesn’t help drive volume down a single highway, and it certainly doesn’t help drive costs down if everyone wants their own specific thing. This is the problem we have with MEMS, as well. MEMS is basically a custom module, and when you look at the supply chain it’s difficult to develop one solution that fits multiple applications. With the interposer, the very high-performance applications can afford the economics of interposer and the whole cost model that goes along with it, even though there’s still a lot of pressure there. But the problem is that limits the amount of volume. There may be a little disconnect because for the HBM, suppliers want to keep the price high. That will not help facilitate tons of volume. The end consumer wants to drive the overall price down. So it’s a combination of the interposer cost plus the HBM. If we aren’t aligned as an industry on how to make this more affordable to the masses, then it’s always going to stay at the very high end. You can see this with the graphics guys. It’s only their very high-end graphics chips that can afford this. Economics is holding everything back. But it’s also aligning the solutions so more applications can adopt the same solution and pave that highway with lower cost.

Kulkarni: The industry will drive the cost. For edge computing, a lot of customers are making decisions right at the edge because there is no time to take that to a central place for processing, whether that’s CPUs or GPUs or HPC farms. So our customers are asking how to serve that base, because it will reduce the IoT nodes in a massive network. For everything from face recognition to traffic jams, decisions have to be made right there. Otherwise, it will cause accidents. The volumes will be huge. From our standpoint, we’re looking at this from a multi-physics perspective, which is the chip-package-system. You cannot take one thing in isolation today, and that’s independent of whether the structures are cost effective. Local problems and global problems are coming together. Take local heat, for example. All of our customers for 2.5D packaging, CoWoS, wafer-on-wafer integration—all of those are heading into thermal management to deal with heat-related effects. ADAS, edge computing, gaming, AI, all cause tremendous switching activity on the chip, at the local register level, as well as globally, which is chip-to-chip. This can create different thermal profiles, which affect signal integrity and noise. The system has to be chip-aware, independent of the configuration. So it’s chip-aware system design, and system-aware chip design. It’s a complete closed loop. In 5G, with beamforming using 4 x 4 MIMOs, there will be thousands of antennas around us to form the beam. But these MIMOs are consuming so much power they have to be developed in the context of what the end goal is, regardless of the cost.

SE: So are you finding the same issues at 7nm as you’re finding at 2.5D? Advanced packaging was supposed to be a way around those types of issues.

Kulkarni: Yes, and it’s getting worse. For dynamic voltage drop, margins previously were quite high. They were in the range of a few milliwatts. For a 0.8V supply, they were in the range of 100 to 150 millivolt margins for dynamic voltage drop. But now the Vdd has gone down to 0.5 to 0.6, while threshold voltages have not gone down, so the margins are very tight. There is hardly any dynamic voltage drop allowed now because things are failing otherwise. We see whole subsystems failing because they didn’t take into account power, thermal, timing, the impact of dynamic voltage drop on timing, and so on. People thought it was a solved problem, but now 5 nanofarad of capacitance can make the difference. And customers don’t know how to find it until they go through the entire system and determine that it won’t work. With a 2.2GHz chip we saw recently, they lost 300MHz of performance because they didn’t account for all of these effects. That’s the Holy Grail for system-in-package and 2.5D to exist.

Lalwani: From our perspective, we’re seeing people running out of I/Os. If that wasn’t a limit, dies would be humongous. That one constraint is driving a lot of what we’re seeing in 2.5D. One of the drivers for chiplets is the sheer inability to maximize your I/O bandwidth. With SerDes, it’s doubled from 28 to 56 to 112, but now, if you want to maximize the number of 112 SerDes, you’re limited by your reticle size unless you come up with creative ways of getting around that problem through advanced packaging. So problems are being solved, but new problems are being created.

Cheung: 7nm enables I/O to toggle faster, but as that happens power consumption increases. That’s an issue. One solution to that is silicon photonics, which is now on the horizon. For advanced packaging, we know the constraints. The biggest challenge is that if you take this back to management, they want to know the ROI. That creates a Catch-22. You need the infrastructure before people will engage it, but on the other hand, that’s a big investment. And when you’re talking to a system designer, they want something that’s predictable. So how do you make your design predictable? For advanced packaging, in my opinion, the EDA industry is very far behind. When we talk to the design community, they say, ‘Show me how to do it.” We have to explain the physics and the interconnects, the thermals, the performance, and the mechanical stuff. But to make it predictable, you need EDA tools.

Kulkarni: To your point, what we’ve been doing for the past 10 years is bringing these multi-physics solutions to solve these issues. We started with electromigration and on-chip ESD (electrostatic discharge). We’re finding a tremendous volume of on-chip ESD in the automotive world. There are a lot of spurious voltages on-chip. Then you have to look at electromagnetics above that. And now, with sub-6GHz 5G, and then going into millimeter wave, we’re dealing with electromagnetic interference, which was largely ignored before. So now you need an on-chip and off-chip electromagnetic radiation analysis and crosstalk analysis, because one event on the chip has six different neighbors that can be impacted by electromagnetics. That is causing failures, especially in the 5G and ADAS world. Then you add other areas, like power integrity and noise integrity, and backtalk voltage impact on timing, which is creating power noise.

Continue reading with part two and part three of this series.

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