tag: crosstalk

PCIe Design Guide – Q&A (Gen 4, 5, 6) – Part 2
By Cadence - 23 Dec, 2025 - Comments: 0

As PCI Express (PCIe) evolves through Gen4, Gen5, and now Gen6, the complexity of high-speed design continues to grow. Signal and power integrity, equalization, clocking, and compliance — every layer of the PCB must be optimized for speed and reliability. The PCIe Design Guide – Q&A (Part 2) expands on the first volume with a deep dive into simulation, validation, and compliance, a... » read more

A Signal Integrity Guide to HSD PCB Design
By Cadence - 27 Aug, 2025 - Comments: 0

As data rates soar into the multi-gigabit range, high-speed digital (HSD) PCB design is no longer just about connecting the dots. Signal integrity (SI) and power integrity (PI) challenges can silently destroy performance—long before your board even hits the lab. This comprehensive guide is your blueprint for mastering SI fundamentals in complex, high-speed PCB systems. From PCIe and DDR t... » read more

3-Channel Package-Scale Galvanic Isolation Interface for SiC and GaN Power Switching Converters
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers" was published by STMicroelectronics and DIEEI, Università di Catania. Abstract "This article presents the design of a three-channel package-scale galvanic isolation interface for SiC and GaN power switching converters. The isolation interface consists of two side-by-sid... » read more

What’s At Stake In System Design?
By Cadence - 08 Mar, 2023 - Comments: 0

What You Will Gain From This eBook: Power and Signal Integrity Insights into harmonic balancing and crosstalk analysis Learning about loop gain and transmission rates Examining the necessity of power-aware systems Electromagnetic Analysis Knowledge about the state of electromagnetics in wireless networks Insight into RADAR and LiDAR EM profiles Tips for bending, meshin... » read more

Parallel Circuit Execution & NISQ Computing
By Technical Paper Link - 02 May, 2022 - Comments: 0

Research from LIRMM, University of Montpellier, CNRS. Abstract "Quantum computing is performed on Noisy Intermediate-Scale Quantum (NISQ) hardware in the short term. Only small circuits can be executed reliably on a quantum machine due to the unavoidable noisy quantum operations on NISQ devices, leading to the under-utilization of hardware resources. With the growing demand to access quan... » read more

PCB Design Rules For Wiring And Crosstalk
By Nikhil Grover - 12 Aug, 2021 - Comments: 0

Today’s electronic devices market demands miniaturized printed circuit boards (PCBs) with a multitude of high-speed functions integrated on a single board. This causes the designers to have traces routed very close to each other to optimize packaging and space. This proximity may cause unintentional coupling of electromagnetic fields, a phenomenon which we know by the name of crosstalk (see f... » read more

Best Practices And Constraint Management Tools Speed RF Design For The IoT
By Jim Martens - 06 Aug, 2020 - Comments: 0

By Jim Martens and David Zima The IoT has increased the demand for good radio frequency (RF) design practices from the mains, to wall outlet power, all the way to the antenna. With several IoT standards employed today, constraint management has become critical to ensuring that designs meet product performance and reliability. Even the simplest of IoT designs can benefit from constraint ma... » read more

Why Chips Are Getting Noisier
By Brian Bailey - 13 Jun, 2019 - Comments: 4

In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Engineering The Signal For GDDR6
By Shawn Nikoukary - 09 May, 2019 - Comments: 0

DDR1 through DDR3 had their challenges, but speeds were below one gigabit and signal integrity (SI) challenges were more centered around static timing and running pseudo random binary sequence (PRBS) simulations. Now, with GDDR6, we are working on 16 to 20 gigabits per second (Gbps) signaling and even faster in the near future. As a result, engineering the signal for GDDR6 will require careful ... » read more

Moore’s Law Now Requires Advanced Packaging
By Ed Sperling - 18 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

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