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Reducing Advanced Packaging Costs

Experts at the Table, Part 2: What’s needed to make different packaging approaches more affordable, and why that may not be a critical factor in the short-term.

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Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEPTEC. To view part one, click here.


(L-R) Chenglin Liu, John Hunt, Eric Tosaya, Juan Rey

SE: How do we get the cost down for advanced packaging?

Hunt: This isn’t just about multiple die. We realized that we can use the same technology we use in heterogeneous integration of multiple die for single-die applications. If we go to 7nm, the cost of the silicon is so high that the customers want to shrink the die. To shrink the die, you often have to shrink the die pad pitch. To do that, you need a higher-cost substrate for a package. So now what we’re doing is using the FoCoS (fan-out chip-on-substrate) technology to fan out that fine pitch on a 7nm die, and putting that on a low-cost substrate. The total cost of that solution is less than using a 7nm die and a high-cost substrate. So you can bring the cost down for advanced packaging even with a single die.

SE: How about for multi-die approaches? Is the solution chiplets or fan-outs or bridges or something else?

Tosaya: Part of the answer depends on the type of device. Is it an I/O-limited design or a logic-limited design? We have seen both. With a device that is I/O-limited, there are a huge number of SerDes. When you are first creating the SerDes design, if you know that you can target a much finer pitch, then you can design the SerDes macro design to support that fine pitch. Whatever you start out with, that will limit your die size if you’re I/O-limited. Knowing the roadmap and what you can utilize a year or two in advance, before you create this SerDes technology for 7nm, is key to being able to improve the cost and design flexibility for this kind of high-performance application.

Hunt: For fan-out solutions, we’re developing a 600mm capability. The systems that we’re intending to put into 600mm will have 2µ lines and spaces capability. So we will be able to do high-density products. ASE also is developing 300mm panel capability. That also can do 2µ lines and spaces. That will allow us to do those solutions at a lower cost because it is much more efficient. You get much more efficient use of lines and spaces in a large panel than a 300mm round application. Economies of scale also will bring it down.

SE: Is that enough to make this approach competitive with other single-chip solutions?

Hunt: The cost will keep coming down over time, not necessarily just because volumes are going up, and you will get efficiencies of scale from the volume increasing. These are very complex technologies. But if we can get rid of silicon interposers and go to fan-out, as long as you can meet your performance requirements, then that’s a great a solution. 2.5D, which is an organic interposer attached to a substrate, could be cost-effective because you have different sources making it. With some significant manufacturing capability improvement, less manufacturing time, and the logistics of the whole supply chain, that’s an attractive concept. Whether that will come to fruition isn’t clear yet.

Rey: Up to three years ago, we were experiencing frustration because 3D or 2.5D were not progressing as fast as we had hoped. Now we are seeing widespread usage. In the shorter term, there are more opportunities. What will come out of these grander research efforts, such as work out of UCLA, we don’t know at the moment. These efforts require massive amounts of research. But they do tend to spin out and promote a bunch of new ideas that become practical over time. Right now, we are seeing more interest than in the past.

Hunt: There is more generalized usage, which will result in a lower cost. We are seeing more and more interest from systems companies because of the performance requirements of AI, and that’s regardless of the cost. So we’re going to see more and more implementations of these packaging approaches, even before the costs go down. Performance is significantly better.

Liu: There is not enough competition right now, and there are not enough people who are capable of designing HBM2 systems. When we get more people who are capable of working with this technology, the volume will go up. So right now a lot of solutions are from the foundry. That will change.

SE: Do the tools and flows exist today to make advanced packaging work? Are there methodologies in place that are as effective as with ASICs, where we can do the necessary exploration and tradeoffs?

Tosaya: To some extent, and that’s why we put the effort into creating a a flow using industry tools to enable it. First of all, without that, there’s a risk. It’s too easy to make mistakes. Second, the resources you have to expend when it’s not automated are extraordinarily high. It takes longer to create a design. In addition, the tools enable much better planning. So if you have 2.5D with a silicon interposer, another option is 2.3D with an organic interposer on a substrate. There are different fan-out technologies. So how do you properly, in a reasonable amount of time, assess those different options for your customers, which of course want the best possible performance solution? You use tools. Today, the typical substrate design is more like a PCB board, with mechanical-driven tools versus the chip-level ASIC design, where you do the LVS and timing analysis. For the high-performance application, we want to move toward the ASIC kind of model. Today, we don’t do that kind of timing analysis for a substrate. We have to break it down, extract pieces, and put it back together. It’s time-consuming and painful, and the tools don’t talk to each other. Now we’re starting to look at timing analysis as part of the overall 2.5D or 3D package module design.

Rey: Tools have been expanded to support a wide range of activities. There has been quite a bit of R&D activity to explore many alternatives, with the expectation that they will come with necessary tools. For example, this includes interactions on the thermal area, including thermal effects on routing and electromigration. There is room for improvement in every area. One of the areas where there is some exciting progress is in the movement from traditional PDK (process design kit) technology that comes from the semiconductor manufacturing area into these ADK (assembly design kit) type of activities, of which we have good examples. It would be great to see much more progress. That’s how we standardize the process.

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