Panel Fan-out Ramps, Challenges Remain

Cost and the lack of a panel-size standard gives fan-out a slower start.


After years of R&D, panel-level fan-out packaging is finally beginning to ramp up in the market, at least in limited volumes for a few vendors.

However, panel-level fan-out, which is an advanced form of today’s fan-out packaging, still faces several technical and cost challenges to bring this technology into the mainstream or high-volume manufacturing. Moreover, several companies are developing the technology using different panel sizes, but there is a need for a standard format. The lack of a panel-size standard makes it difficult for equipment makers to commit resources and develop systems for panel fan-out.

In production for several years, today’s fan-out technologies involve packaging a die in a round wafer format in 200mm or 300mm wafer sizes. TSMC’s InFO technology, the most notable example of fan-out, is being used in Apple’s latest iPhones.

In panel-level fan-out, though, the package is processed on a large square panel. In one theoretical example, a 500mm x 500mm panel can process 4.54 times as many die as a 300mm wafer, according to a recent paper from STATS ChipPAC and Rudolph Technologies. By increasing the number of die per substrate, a vendor could see huge productivity gains and lower costs over today’s fan-out processes.

Fig. 1: Comparison of number of die exposed on 300mm wafer to number of die on panel. Source: STATS ChipPAC, Rudolph

Today, roughly a half-dozen companies are working on panel fan-out. A few are in limited production, while others have pushed out the technology as demand is taking longer than expected. Others are still in R&D, while some are not pursuing it.

Panel fan-out won’t replace today’s wafer-level fan-out in the foreseeable future, and it will not be used for all applications. The technology makes sense for high-volume products, but not for smaller lots.

Both low- and high-volume products also can run on wafer-level fan-out. So there might be some overlap, if not competition, between wafer and panel fan-out for high-volume products. For customers, though, it doesn’t matter what technology a package uses as long as it meets certain cost and reliability specs. If panel fan-out or any package type doesn’t meet certain criteria, OEMs won’t use it.

The big issue is that few, if any, products require panel fan-out today, so the technology may not reach high-volume manufacturing until 2020, which is a year later than expected.

“The volumes are low now. These new technologies take a while,” said Jan Vardaman, president of TechSearch International. “You have to find the right application for panel. You need a single product with high volumes to justify panel, so we might not need it until 2020 for most applications.”

Others agree. “There are still issues for a wider adoption,” said Santosh Kumar, director and principal analyst for package, assembly and substrates at Yole Développement. “I see it becoming more mainstream in 2020.”

Still, customers must keep a close eye on panel fan-out as several major events have recently taken place. Among them:

  • Samsung Electro-Mechanics (SEMCO) has invested $400 million in the technology, according to Yole. SEMCO recently rolled out the first products from its panel-level production line, a fan-out package for Samsung’s new smartwatch.
  • Nepes hopes to ramp up panel-level fan-out in 2018, while the ASE/Deca duo plan to move into production in late 2019 or 2020.
  • Powertech recently announced a $1.6 billion, panel fan-out plant in Taiwan with plans to move into production by 2020.
  • JCET/STATS and Unimicron are also developing the technology with plans to ship it sometime after 2020, according to Yole.

TSMC has no plans to develop panel fan-out, saying that wafer-level fan-out meets all requirements. And Intel, which has a panel-level production line, did not disclose its product plans.

Fig. 2: Who is doing what in panel fan-out. Source: Yole Développement

Wafer vs. panel
In total, the overall fan-out market is expected to grow 20% between 2018 and 2023, reaching $2.3 billion by 2023, according to Yole. Of that, the panel fan-out market is expected to grow by 79% from 2017 to 2023, reaching $279 million by 2023, according to Yole.

Originally introduced in the mid-2000s, fan-out is different than conventional IC-packaging. Traditionally, the individual chips on a wafer are diced and then undergo a packaging process.

Conventional packaging has some pluses and minuses. For example, one popular type, called quad flat pack (QFP), is cheap, but it can take up valuable real estate on the board.

Meanwhile, in fan-out, the dies are packaged while on a wafer, which is a process called wafer-level packaging (WLP). The same is true for a related package called fan-in. In WLP, the resulting package is roughly the same size as the chip itself, which saves space on the board.

Neither fan-in or fan-out requires an interposer like 2.5D/3D technologies, but the two WLP package types are slightly different. One distinction is how the two package types incorporate the redistribution layers (RDLs). RDLs are the copper metal connection lines or traces that electrically connect one part of the package to another. RDLs are measured by line and space, which refer to the width and pitch of a metal trace.

In fan-in, the RDL traces are routed inwards. Fan-in is limited and runs out of steam at about 200 I/Os and 0.6mm profiles.

But in fan-out, the RDLs are routed inward and outward, enabling thinner packages with more I/Os. “In fan-out, you expand the available area of the package,” said John Hunt, senior director of engineering at ASE.

In the fan-out process flow, the chips are processed on a wafer in the fab and then diced at the packaging house. Using a pick-and-place system, the dies are placed on a wafer-like format based on an epoxy molded compound. This is referred to as a reconstituted wafer.

This wafer can be processed in either a 200mm or 300mm round format. The fan-out manufacturing process, such as the formation of the RDL layers, is conducted on the reconstituted wafer. Then, the dies are cut, forming a chip housed in a fan-out package.

There are three different types of fan-out processes—chip-first/face-down, chip-first/face-up, and chip-last.

Fig. 3: Chip first vs. chip last. Source: TechSearch International.

Today, Amkor, ASE, JCET/STATS, TSMC and others are in production with fan-out. Apple, Infineon, NXP, Qualcomm and others are using fan-out.

The main applications for fan-out include audio codecs, connectivity, MCUs, power management ICs (PMICs) and RF. Now, fan-out is moving into 5G, automotive and other applications.

Automotive is a big driver. “Global car production CAGR is about 2% per year. The electronic content is expected to double by the time you get to 2025,” said Jacinta Aman Lim, deputy director at JCET/STATS ChipPAC, during a presentation at the recent IWLPC event. For fan-out, “there is a huge market in automotive for mmWave. A lot of this is ADAS radar.”

Not all chips are using fan-out. For many applications, fan-out is too expensive or not required, and instead, customers use a variety of cheaper packages.

To get broader adoption of fan-out, the industry continues to drive down the cost of the technology. Another possible way to reduce the cost is to move towards a panel-level production process, called panel-level fan-out.

In simple terms, a panel can process more packages than a wafer, thereby lowering the cost for both single- and multi-die packages.

Panel-level packaging isn’t new, though. Starting in 2011, several vendors introduced panel-level fan-out, but most of those efforts failed as the processes were immature.

Now, the industry is developing next-generation panel fan-out. Vendors face many of the same challenges as before, although the technology appears to be more feasible.

“ASE is doing all forms of wafer-level fan-out,” said Hunt. “We’re seeing in the next year or so that volumes will increase significantly. We’re putting in panel capability because it can handle higher volumes with less equipment costs. It saves the customer money.”

Panel fan-out is targeted for the same applications as wafer fan-out. “That’s PMICs, RF and other single-die applications, followed by multi-die applications,” Hunt said.

The economics for panel are complicated, however. For example, a 300mm wafer can handle 2,500 6mm x 6mm packages on the same substrate. In comparison, a 600mm x 600mm panel can handle 12,000 packages.

It doesn’t make sense to run small lots on a panel. If the total area of the panel isn’t fully utilized, it translates into wasted materials and a loss.

So, for smaller lots, it makes more sense to use wafer-level fan-out. For high-volume devices, though, panels make more sense.

“There is a perception in the industry that when panel fan-out comes out, everybody is going to save money on packaging. That is not true,” Hunt said. “So, who do you think will save money? Only the companies that can run huge volumes. There are a lot of customers that will never have the volume to fill a panel line. But we see some customers and some products that will ramp up for a large panel.”

Looking at the issues from another angle, Fraunhofer devised a cost model that compares wafer- and panel-level fan-out.

Panel fan-out has more surface area than wafer fan-out, which translates into a cost advantage. The area utilization for panel is ≥95% without a package size limitation, according to Fraunhofer. In comparison, the highest area utilization for wafer fan-out is 88%, but that figure drops to 45% for larger packages, according to Fraunhofer’s Institute for Reliability and Microintegration.

In another example, Fraunhofer calculated the amount of epoxy molding compound (EMC) used and lost for different package sizes during the production of 15 million packages. EMC is an expensive material used in wafer and panel fan-out.

For a 30mm x 30mm package, the EMC loss is more than two tons on a round wafer, according to Fraunhofer. This loss can be decreased by around 77% using a 457mm x 610mm panel, according to the R&D organization.

“In conclusion, panel-level processing represents a considerable opportunity to reduce material waste and substantially supports a more cost-effective production by higher area utilization,” said Tanja Braun, deputy group manager at Fraunhofer.

The challenges
Still, panel-level fan-out faces some challenges, namely the lack of a panel-size standard. The industry is developing the technology using various panel sizes, such as 300mm x 300mm, 457mm x 610mm, 510mm x 515mm, 600mm x 600mm and others.

Each vendor has a different idea when it comes to the panel size, but the lack of standards creates a headache for the equipment industry.

Some equipment vendors have developed tools for panel-level fan-out, although many others aren’t jumping into the market for several reasons. Most don’t have the resources to support all panel sizes. Tool vendors could build a system that supports a panel size or two. Yet it’s not feasible to sell only a few tools to a limited customer base, so many are waiting on the sidelines until a standard size emerges and the market takes off.

Simply put, the industry needs a panel-size standard. “We need to come up with some standards, so we can get equipment manufacturers engaged and start driving the cost of some of these processes and tools down,” said Tom DeBonis, an engineering manager for the Assembly Test Technology Development group at Intel.

In response, SEMI is trying to develop a panel-size standard. Recently, SEMI’s FO-PLP Panel Task Force formulated a ballot process to vote on a standard.  The initial ballot narrowed the panel options to two sizes—510mm x 515mm and 600mm x 600mm.

“Based on feedback received on this ballot, the Task Force will modify the specification with the objective of focusing on a single panel size as well as adding tolerance and orientation requirements,” according to FO-PLP Panel TF leaders Cristina Chu and Richard Allen. Chu is a marketing director at ASM-NEXX, while Allen is a physicist at NIST.

“The updated version of the ballot will be finalized during meetings in November and December. The Task Force will then re-ballot the specification in Cycle 1 of 2019, which opens in mid-January. We are hoping this standard gets approved in the spring of 2019 and is published by summer 2019,” according to Chu and Allen.

It’s unclear if the industry will agree upon a standard, however. Besides the standards issues, panel-level fan-out has many of the same technical challenges as wafer-level fan-out. The big challenges for panel include die shift, warpage, RDL formation and handling.

As stated, in fan-out, a round wafer is formed by using an epoxy mold compound, which creates a reconstituted wafer. The dies are placed on the wafer and the placement accuracy of the dies is critical. But at times, the dies move during the process, causing an unwanted effect called die shift.

“The other technical challenges include warpage management and fabrication of high-density RDLs at 5-5μm and below,” Yole’s Kumar said. “Moving from wafer to panel size also doesn’t make all process steps scalable. Molding and lithography are scalable, but pick-and-place is a serial process and a big bottleneck for high yield. This requires a high unit per hour (UPH) and accurate die bonder that can reduce the die placement time on a large panel. Such die bonders are available in the market but are expensive.”

There are also several process control issues. “The main challenges for both process and process control tools is the need for large panel handling (up to 600 x 600mm) with the ability to handle high warpage (>10mm), and to meet the requirements to deliver performance (e.g. uniformity, precision, accuracy, etc.) across the far larger substrates than 300mm wafers,” said Pieter Vandewalle, general manager of the ICOS Division at KLA-Tencor.

“Similar to wafer-level packaging, the panel-level process control challenges include CD metrology, defect inspection, as well as RDL and bump inspection and metrology. Current panel-level specs are less advanced; however, we believe this will follow a similar evolution as wafer-level packaging. When the panel process reaches a mature state, the line/space dimensions will also be <2µm. For finished fan-out packages, the thickness and the warpage are also very critical. We are observing a greater need for 6-side inspection, including measurements of total package height, high-accuracy warpage and coplanarity,” Vandewalle said.

Meanwhile, today’s wafer-level fan-out is moving towards RDLs at 2-2μm line/space with 1-1μm or below in R&D. In comparison, panel fan-out is around 10μm line/space or so.

“Right now, fan-out on the wafer level is probably capable of finer lines and space in volume production than fan-out in panel,” Intel’s DeBonis said. “What we would like to see is that gap closed. Then, you can put it in additional applications and do more heterogeneous integration.”

The line/space constraints could limit the applications for panel fan-out. “A large-size panel is hard to maintain good planarity. That gives you a big constraint to go to high-performance products,” said Doug Yu, vice president of R&D at TSMC. “So, with panel, you end up competing with relatively lower end, simpler and smaller packages like PMICs and codecs. In those areas, there is already a lot of built wafer capacity.”

Who is doing what
Still, the industry is moving full speed ahead with the technology despite the challenges.

In June, SEMCO rolled out the first fan-out packages from its new panel production line. Used for Samsung’s smartwatch, the package combines an application processor with a PMIC. It features three layers of RDL with a backside layer at 7μm-8μm line/space.

“The reason why we need to use panel is because it is economically feasible. Simultaneously, it is better for fan-out SIP,” said Kwang Wook Bae, vice president at SEMCO.

Meanwhile, South Korea’s Nepes is also ready for production as it recently completed a panel-level fan-out line using a 600mm x 600mm format.

In Taiwan, meanwhile ASE is developing two panel-level technologies. The first is a chip-last fan-out process using a 300mm square panel.

Then, ASE is also working on both wafer- and panel-level fan-out, based on the technology from Deca. ASE will soon move into production with wafer-level fan-out, based on this technology.

Using the same technology from Deca, ASE plans to ramp up panel fan-out in late 2019 with production slated for 2020. That schedule could change, depending on demand.

For this, ASE is using a 600mm x 600mm panel, but it isn’t processing the entire panel at once. Instead, ASE divides the panel into four 300mm quadrants. The processing is conducted on each quadrant and each area can accommodate different packages.

“Our backend and probing equipment that handles 300mm round will handle 300mm square with minimal modifications. So, we don’t have to go and develop new equipment vendors for the probing and backend processing,” ASE’s Hunt said.

Meanwhile, Taiwan’s Powertech has big plans in the arena. Then, Hong Kong’s ASM Pacific recently launched a consortium, dubbed the Fan-Out Wafer/Panel-Level Packaging (FOW/PLP) Consortium. The group includes Dow, Huawei, Indium, JCAP and Unimicron.

ASM Pacific’s group uses a 508mm x 508mm panel. “Even the dry film EMC is by lamination. It is a pure PCB technology. Also, it is a low-cost, low-profile, and high-throughput fan-out technology,” said John Lau, senior technical advisor at ASM Pacific. “In order to have a very high-throughput and low-profile package and save the EMC, a process called Uni-SIP (unisubstrate-integrated-package) is used to fabricate the RDLs.”

To be sure, panel-level fan-out holds a lot of promise to bring down the cost of packaging, but it’s still in the early stages of development.

But based on the current supply/demand picture, there might be too many panel fan-out vendors and not enough customers, meaning the market may see a shakeout over time. There is probably room for only a few players in what is still an uncertain market.

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