Toward High-End Fan-Outs

Denser interconnects, stacked die could rival 2.5D approaches.


Foundries and OSATs are working on more advanced fan-outs, including some with vertically stacked die inside the package, filling a middle ground between lower-cost fan-outs and systems in package on one side and 2.5D and 3D-ICs on the other.

These new fan-outs have denser interconnects than previous iterations, and in some cases they include multiple routing layers stacked on top of each other. TSMC has been offering this stacking capability for months with its Integrated Fan-Out (InFo), and now some OSATs are stepping in with their own versions.

Until very recently, fan-outs were seen almost entirely as the low-cost advanced packaging option, basically shrinking components that would otherwise be found on a PCB and putting all of them inside a single package. There are a number of advantages to this approach. First, putting everything into a smaller package reduces material costs. Second, by shortening distances that signals have to travel compared with a larger, fully integrated SoC, performance goes up while the amount of power needed to drive those signals goes down. And third, by combining chips developed at different nodes into the same device, chipmakers can optimize floor-planning to minimize physical effects such as cross-talk, power noise and electromigration.

This doesn’t mean work on low-end fan-outs is decreasing. In fact, the opposite is true. New EDA tools and flows are being developed and introduced, and so are panel-level packaging approaches for devices with sufficient volume. But high-end fan-outs push this packaging approach in a new direction, where the emphasis is on reducing lines and spaces for higher density, as well as significantly improving performance. While most fan-outs have lines and spaces above 8μm, those numbers could be as low as 2μm for these new devices. (Lines and spaces are the width and pitch of a metal trace.)

Fig. 1: Low-density versus high-density fan-outs. Source: ASE/SEMI Industry Strategy Symposium

“Everyone was thinking of fan-out for low-end solutions, but we see it as a high-end solution, as well,” said John Hunt, senior director of engineering at Advanced Semiconductor Engineering (ASE). “You can do a fan-out with a chip up and another chip directly on top of that. That’s very good for photonics because they want it within 50 microns. You also can use the fan-out as a die substrate alternative, so you flip the chip around onto the package. That allows you to transfer heat down as well as up.”

Hunt said that fan-out chip-on-substrate, which basically combines multiple routing layers on a substrate, also can replace 2.5D for some applications. “One of the great things about fan-out approaches is there is not as much stress on the individual dies. This isn’t going to replace high-density silicon interposer, but it will come in at a lower-cost and it allows companies to re-use silicon.”

Fig. 2: Multi-layer routing in a fan-out chip-on-substrate. Source: ASE/ISS

High-end fan-outs also add a novel approach to dealing with thermal issues that have plagued vertical stacking. With monolithic 3D stacking, if one of the logic layers is packaged between two other layers, it’s difficult to get the heat out of the middle logic layer without some exotic cooling technology such as microfluidics. That typically results in the partial or total shutdown of the sandwiched logic, and limits the benefits of this kind of packaging. But with double-sided cooling, particularly with fan-out on substrate, thermal issues can be managed more easily.

“InFO will continue in its current form as an integrated memory pre-stacked package solution for the Apple processor,” said Ron Huemoeller, corporate vice president for R&D at Amkor. “Beyond that, it remains to be seen how far the current format will extend. Fan-out on substrate will be the new hot button for the industry, introduced in varying forms from low density to high density fan out on substrate.”

New markets
Fan-outs went mainstream in 2016, when Apple adopted TSMC’s InFO technology for the application processor in the iPhone 7. Since then, fan-outs have been used in a variety of applications ranging from high-volume consumer devices such as phones to automotive applications, where time to market, flexibility and performance are critical.

Automotive is a particularly attractive opportunity for advanced packaging because there is so much uncertainty about how chips such as sensors and sensor hubs will ultimately look and what protocols they will have to support. Technology is still evolving for these applications, which means that what gets developed today may have to be modified much more quickly than in the past. Automotive design cycles used to be five to seven years for electronics. It is now on the same rollout schedule as consumer electronics.

Advanced packaging can help in this regard. It makes it simpler to augment existing designs with some new components, including different memories or memory configurations, as well as additional features that may not be available when a device is originally designed. In these cases, advanced packaging essentially creates a platform on which new functionality can be added without having to re-do the entire design. At least some of those now involve chips that are stacked vertically as well as horizontally.

Fig. 3: Fan-out revenue forecast by market type. Source: Yole Développement.

“We’ve seen this with MEMS devices, where ASICs and MEMS sensors are stacked on top of each other,” said Ram Trichur, director of business development for Brewer Science‘s Advanced Packaging Unit. “It’s also being looked at for high-frequency applications, greater than 24 GHz, where the antenna link needs to be the size of the package. With 5G, there are severe losses because of the frequency, so you need to decrease the distance between the different functional parts. With 4G LTE, the antenna link was a flexible cable off the chip. With 5G and millimeter wave, the antenna length is a few millimeters, so it needs to be integrated into the package.”

Not so simple
Fan-outs have been under development for more than a decade. So far, there is no single approach that works for everything. Even at the high end of this market there are a number of different varieties, including fan-out on substrate and package-on-package fan-out, as well as chip-first or chip-last approaches.

“Fan-out is a very good technology for low-cost and mid-cost applications,” said Andy Heinig, research engineering at Fraunhofer EAS. But we also see technology limits for fan-out. You can put two to three routing layers on fan-outs, but at this point 95% have been down with only one routing layer. With two layers, the yield decreases. And in the end, if you don’t have 98% to 99% yield, the design doesn’t go into production.”

Heinig noted that one approach is to develop the fan-out layers, put the chip into molding. This so-called chip-last approach is more flexible and simpler than starting with a chip first. But if more routing layers are added, the fan-out cost increases and the yield goes down, at least initially. And by the time all the factors are taken into account, it may be comparable to the cost of an interposer.

“For high-end applications, fan-out still cannot reach the requirements for HBM,” he said. “Bridges are another alternative, but they have some limitations, too. This involves a small piece of silicon which is put in between the processor and memory. If you have 1 HBM stack and one processor, you can align the processor and the memory with a bridge. But if you have four HBM stacks, there’s a problem aligning that with a bridge. So you can cut the cost of silicon, but there are a lot of steps to align the bridge. That makes it more expensive to develop, and in the end it may be more expensive than 2.5D.”

So at least for the time being, both 2.5D and high-end fan-outs will continue to overlap.

“2.5D will continue its slow growth in the HPC and automotive sector for specific applications,” said Amkor’s Huemoller. “Graphics is a main driver still, but multi-logic configurations will also require 2.5D packaged structures to address the AI market, as well. Multi-die products will drive the packaging industry going forward with new product growth. Heterogeneous integration will fully deploy in multiple formats over the next couple of years, including SiP, sub-system modules, 2.5D and various silicon-to-silicon bridge concepts. The incorporation of mixed technologies in modular form will drive much of this.”

Industry buy-in
No matter how difficult advanced packaging is, it’s still simpler and less expensive than putting everything onto an SoC developed at the most advanced nodes. While short-channel effects, which are responsible for leakage current, were reduced at 16/14nm with the introduction of finFETs, leakage is increasing again at 10/7nm. Gate-all-around FETs have been proposed beyond that, but the cost is expected to increase significantly as new transistor types are added into the mix, along with EUV lithography.

“There is still a push to continue integrating at smaller nodes,” said Navraj Nandra, senior director of marketing for the DesignWare Analog and MSIP Solutions Group at Synopsys. “At the same time, people are coming up with packaging solutions-either side by side or stacked die using TSVs or interposer. That’s becoming real. Packaging costs are low enough that it’s worthwhile developing products without crazy high expenses. Part of what’s driving that is deep neural networks, convolutional neural networks and machine learning, particularly on the inferencing side.”

This doesn’t displace scaling. But it does provide an alternative, as well as a possible way of extending scaling. And while this isn’t necessarily the cheapest solution, it can certainly be less costly than trying to develop everything at the latest node, such as analog sensors or PHYs.

“Advanced packaging is more for performance reasons or power reduction reasons and form factor more than cost,” said Rick Gottscho, chief technology officer at Lam Research. “It doesn’t displace scaling and trying to get higher density at the chip level. It’s complementary, and both will keep going. It certainly doesn’t replace the shrink approach to scaling.”

Mark Dougherty, vice president of advanced module engineering at GlobalFoundries, agrees. “It comes back to working things in parallel,” Dougherty said. “If you look at through-silicon vias, and 2.5D and 3D, it becomes a very application-specific question. It won’t obviate the need to scale at the die level, but depending on the solutions that the end customer is looking for, it opens up a lot more possibilities there. There is certainly the case of marrying logic with DRAM, or one technology generation with another. All of those things are happening. But it more will be driven by the application space.”

The number of packaging options available continues to grow. While that adds a fair amount of confusion, it’s also a sign that device scaling alone is getting too expensive and complex to continue every couple of years. Instead of moving to half-nodes, those continuing on the road map are jumping ahead to the next full node, and they are looking to extend that further with architectural options beyond a single planar die.

In that context, higher-performance, denser fan-outs are yet one more option that chipmakers increasingly are considering and adopting. Whether this is the beginning of more 3D integration, or simply a new alternative to platforms isn’t entirely clear yet. But packaging is becoming more complicated and much more customizable, and that trend is likely to continue for the foreseeable future.

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DrFlipChip says:

Adv. Packaging ( more precisely Dense Off Chip Integration or DOCI ) has its inherent limits & challenges too. In the interest of performance, form factor and cost, various components ( semiconductors, conductors / interconnects / wave guides, dielectrics ) with incompatible thermo mechanical properties are tightly integrated into a “laminate” w/ no one dominant material. As a result the whole laminate can warp due to elevated temperatures used during assembly, throwing features that need to mate out of planarity and alignment. Fatigue stresses due to thermal cycling during service can cause failures and limit life. Which is why there is now a lot of interest in Glass substrates that have CTE compatible with Si yet lower electrical losses. But creating 2 um L/S interconnects using conventional semi additive process that we developed over 25 years ago for Wafer Bumping & Organic Substrates is still problematic due to undercuts during etching the seed layer. Using laser writing & CMP to create 2 um L/S on Substrates or RDL on FO WLPs drives the cost up to almost the same as 2.5 d Si Interposers w/ Dual Damascene Cu.

For your next article on Adv. Packaging ( / DOCI ) why not first verify the actual L/S on these claims ( e,g. by requesting the Vendors for SEM cross sections w/ um markers ). Qualification data on yield & reliability would be good reality checks too.

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