tag: high-bandwidth memory

HBM-Enabled FPGA-Based Graph Processing Accelerator
By Technical Paper Link - 19 Feb, 2023 - Comments: 0

A technical paper titled "ACTS: A Near-Memory FPGA Graph Processing Framework" was published by researchers at University of Virginia and Samsung. Abstract: "Despite the high off-chip bandwidth and on-chip parallelism offered by today's near-memory accelerators, software-based (CPU and GPU) graph processing frameworks still suffer performance degradation from under-utilization of available ... » read more

Advanced Packaging for High-Bandwidth Memory: Influences of TSV size, TSV Aspect Ratio And Annealing Temperature
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A technical paper titled "Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications" was published by researchers at National Yang Ming Chiao Tung University. Abstract: "The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for ... » read more

Where Power Is Spent In HBM
By Ed Sperling - 06 Feb, 2023 - Comments: 0

HBM is gaining ground because of a spike in the amount of data that needs to be processed quickly, but big reductions in power are possible if that processing can be moved closer to the HBM modules, and if more can be done in each compute cycle without sending data back and forth to memory as frequently. Steven Woo, fellow and distinguished engineer at Rambus, talks about what can be done to bo... » read more

HBM-based scalable multi-FPGA emulator for Quantum Fourier Transform (QFT)
By Technical Paper Link - 01 Jul, 2022 - Comments: 0

New technical paper titled "A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory" from researchers at Tohoku University in Japan. Abstract: "Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum computers do not... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II
By Rahul Singhal - 08 Mar, 2022 - Comments: 0

By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

It’s Official: HBM3 Dons The Crown Of Bandwidth King
By Frank Ferro - 10 Feb, 2022 - Comments: 0

With the publishing of the HBM3 update to the High Bandwidth Memory (HBM) standard, a new king of bandwidth is crowned. The torrid performance demands of advanced workloads, with AI/ML training leading the pack, drive the need for ever faster delivery of bits. Memory bandwidth is a critical enabler of computing performance, thus the need for the accelerated evolution of the standard with HBM3 r... » read more

Advanced Packaging For Automotive Chips
By Ann Mutschler - 02 Dec, 2021 - Comments: 0

Multiple types of chips may be better than one for dealing with large amounts and different types of data, but in automotive applications it's not entirely clear how or even whether they should be packaged together. The biggest problem with electronics in vehicles is the extreme range of temperatures, both within and outside of vehicles. Without adequate cooling, chips can age prematurely, s... » read more

Fan-Out And Packaging Challenges
By Mark LaPedus - 06 Oct, 2021 - Comments: 2

Semiconductor Engineering sat down to discuss various IC packaging technologies, wafer-level and panel-level approaches, and the need for new materials with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of globa... » read more

Will Monolithic 3D DRAM Happen?
By Bryon Moyer - 09 Sep, 2021 - Comments: 1

As DRAM scaling slows, the industry will need to look for other ways to keep pushing for more and cheaper bits of memory. The most common way of escaping the limits of planar scaling is to add the third dimension to the architecture. There are two ways to accomplish that. One is in a package, which is already happening. The second is to sale the die into the Z axis, which which has been a to... » read more

Fan-Out Packaging Options Grow
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

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