tag: high-bandwidth memory

The Hunt For A Low-Power PHY
By Brian Bailey - 17 Apr, 2017 - Comments: 0

Physics has been on the side of chipmakers throughout most of the lifetime of [getkc id="74" comment="Moore's Law"], but when dealing with the world outside the chip, physics is working against them. Pushing data at ever-faster rates through boards and systems consumes increasing amounts of power, but the power budget for chips has not been increasing. Could chips be constrained by their int... » read more

HBM2: It’s All About The PHY
By Bill Fuller - 09 Mar, 2017 - Comments: 0

HBM DRAM is currently used in graphics, high-performance computing (HPC), server, networking and client applications. HBM, says JEDEC HBM Task Group Chairman Barry Wagner, provides a “compelling solution” to reduce the IO power and memory footprint for the most demanding applications. Recent examples of second-generation HBM deployment include NVIDIA’s Quadro GP100 GPU which is paired wit... » read more

2.5D Adds Test Challenges
By Jeff Dorsch - 06 Mar, 2017 - Comments: 0

OSATs and ATE vendors are making progress in determining what works and what doesn't in 2.5D packaging, expanding their knowledge base as this evolves into a mainstream technology. A [getkc id="82" kc_name="2.5D"] package generally includes an ASIC connected to a stack of memory chips—usually high-bandwidth memory—using an [getkc id="204" kc_name="interposer"] or some type of silicon bri... » read more

The Challenges Of Designing An HBM2 PHY
By Frank Ferro - 09 Feb, 2017 - Comments: 1

Originally targeted at the graphics industry, HBM continues to gain momentum in the server and networking markets as system designers work to move higher bandwidth closer to the CPU. Expanding DRAM capacity – which boosts overall system performance – allows data centers to maximize local DRAM storage for wide throughput. HBM DRAM architecture effectively increases system memory bandwidth... » read more

Performance Increasingly Tied To I/O
By Ed Sperling - 18 Jan, 2017 - Comments: 0

Speeding up input and output is becoming a cornerstone for improving performance and lowering power in SoCs and ASICs, particularly as scaling processors and adding more cores produce diminishing returns. While processors of all types continue to improve, the rate of improvement is slowing at each new node. Obtaining the expected 30% to 50% boost in performance and lower power no longer can ... » read more

Smart Manufacturing Gains Momentum
By Ed Sperling - 05 Jan, 2017 - Comments: 0

Smart manufacturing is gaining traction as a way of addressing increased market fragmentation while still leveraging economies of scale. The goal is to add a level of flexibility into manufacturing processes that until recently was considered impossible. Although the approach makes sense in theory, real-world implementation is proving far from consistent. Sometimes referred to as Industr... » read more

Stacked Die Changes
By Ed Sperling - 27 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of tha... » read more

Architecting Memory For Next-Gen Data Centers
By Frank Ferro - 26 Jul, 2016 - Comments: 2

The industry’s insatiable appetite for increased bandwidth and ever-higher transfer rates is driven by a burgeoning Internet of Things (IoT), which has ushered in a new era of pervasive connectivity and generated a tsunami of data. In this context, datacenters are currently evaluating a wide range of new memory initiatives. All seek to optimize efficiency by reducing data transport, thus sign... » read more

The Future Of Memory
By Ed Sperling - 16 Jun, 2016 - Comments: 2

Semiconductor Engineering sat down to discuss future memory with Frank Ferro, senior director of product management for memory and interface IP at [getentity id="22671" e_name="Rambus"]; Marc Greenberg, director of product marketing at [getentity id="22035" e_name="Synopsys"]; and Lisa Minwell, [getentity id="22242" e_name="eSilicon"]'s senior director of [getkc id="43" kc_name="IP"] marketing.... » read more

One-On-One: Dave Hemker
By Ed Sperling - 19 May, 2016 - Comments: 0

Dave Hemker, CTO at [getentity id="22820" comment="Lam Research"], sat down with Semiconductor Engineering to look at some of the key issues on the process and manufacturing side, and some of the key developments that will reshape the semiconductor industry in the future. What follows are excerpts of that conversation. SE: One of the big discussion topics these days is [getkc id="208" commen... » read more

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