Chip Industry Week In Review


By Adam Kovac, Gregory Haley, and Liz Allan. The U.S. government released a 61-page report, titled "National Strategy on Microelectronics Research,” by the Subcommittee On Microelectronics Leadership. It provides a framework for government, industry, academia, and international allies to address four major goals. Synopsys  acquired Intrinsic ID, which develops physical unclonable func... » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan Renesas will acquire Transphorm, which designs and manufactures gallium nitride power devices, for about $339 million. GaN, which is a wide-bandgap technology, is used for high-voltage applications in a slew of markets, including EVs and EV fast chargers, as well as data centers and industrial applications. Cadence acquired Invecas, a provider o... » read more

Next Steps For Panel-Level Packaging


Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel-level processing. Fraunhofer IZM recently announced a new phase of its panel-level packaging consortium. What follows are excerpts of that discussion. SE: IC packaging isn’t new, but years a... » read more

Week In Review: Manufacturing, Test


Chipmakers Chip investments in Malaysia got a shot in the arm this week. First, Intel has announced plans to invest more than RM30 billion, or US$7 billion, within its Malaysian packaging and test facilities. The additional investment will help expand Intel Malaysia’s operations across Penang and Kulim. This new investment is expected to create over 4,000 Intel jobs as well as over 5,000 con... » read more

Week In Review: Manufacturing, Test


Chipmakers TSMC posted its results for the quarter and confirmed its long-awaited plans to build a fab in Japan. It’s not a leading-edge fab, but rather a plant for 28nm/22nm processes. “The company confirmed plans to build a new fab in Japan for 22nm + 28nm,” said Aaron Rakers, an analyst at Wells Fargo, in a research note. “An average 22/28nm fab costs ~$4-5B range per 45k wspm. Fab ... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Micron will cease development of 3D XPoint, a next-generation memory technology. Micron also plans to sell a fab that produces 3D XPoint chips. For some time, Intel and Micron have co-developed 3D XPoint, which is based on phase-change memory technology. Intel sells solid-state storage drives (SSDs) using 3D XPoint. In a fab located in Utah, Micron is producing this memo... » read more

Planning For Panel-Level Fan-out


Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Week In Review: Manufacturing, Test


Packaging and test In a major deal that has some implications in the OSAT supply chain, South Korea’s Nepes has taken over Deca Technologies’ wafer-level packaging manufacturing line in the Philippines. In addition, Nepes has also licensed Deca’s M-Series wafer-level packaging technology. This includes fan-in technology as well as wafer- and panel-level fan-out. It also includes an ad... » read more

Week In Review: Manufacturing, Test


Chipmakers In its latest move to cut costs and focus on its core business, GlobalFoundries (GF) has announced plans to jettison its U.S. photomask operations in Burlington, Vt., but the foundry vendor will maintain a stake in its joint venture mask unit. Under the plan, Toppan Photomasks will acquire certain assets of GF’s Burlington photomask facility. “GF is transferring its mask tool... » read more

Manufacturing Bits: June 25


Panel-level consortium Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging. In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on ... » read more

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