Fan-Out Panel-Level Packaging Hurdles


Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield. There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in ve... » read more

Many More Hurdles In Heterogeneous Integration


Advanced packaging options continue to stack up in the pursuit of “More than Moore” and higher levels of integration. It has become a place where many high-density interconnects converge, and where many new and familiar problems need to be addressed. The industry’s first foray into fine-pitch multi-die packaging utilized silicon interposers with through-silicon vias (TSVs) to deliver s... » read more

Reducing Advanced Packaging Costs


Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEP... » read more

The Process Design Kit: Protecting Design Know-How


Once upon a time, integrated circuits (ICs) were built by the same companies that designed them. The design of an IC was tightly integrated with the manufacturing processes available within each company. In these days, when designs contained hundreds of transistors, companies modeled each feature in an IC at a first principles level, meaning each transistor or fundamental device was analyzed an... » read more