Chiplets Need A New Workflow

By Ann Mutschler - 14 May, 2026 - Comments: 0

Key Takeaways: Chiplet design turns semiconductor development into a system-level problem, requiring coordinated workflows across design, packaging, verification, test, and reliability. Successful chiplet workflows must handle multi-physics challenges — especially thermal, mechanical, power, and signal integrity — early enough to reduce costly failures before assembly and tape-out. ... » read more

Catching Critical Defects In TSVs And Stacked Chips

By Laura Peters - 10 Feb, 2026 - Comments: 0

Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

AI Pushes High-End Mobile From SoCs To Multi-Die

By Liz Allan - 08 Jul, 2025 - Comments: 0

Advanced packaging is becoming a key differentiator for the high end of the mobile phone market, enabling higher performance, more flexibility, and faster time to market than systems on chip. Monolithic SoCs likely will remain the technology of choice for low-end and midrange mobile devices because of their form factor, proven record, and lower cost. But multi-die assemblies provide more fle... » read more

Chiplet Tradeoffs And Limitations

By Ann Mutschler - 10 Apr, 2025 - Comments: 0

The semiconductor industry is buzzing with the benefits of chiplets, including faster time to market, better performance, and lower power, but finding the correct balance between customization and standardization is proving to be more difficult than initially thought. For a commercial chiplet marketplace to really take off, it requires a much deeper understanding of how chiplets behave indiv... » read more

Rethinking Design, Workflow For 3D

By Karen Heyman - 26 Oct, 2023 - Comments: 0

In the 3D world, where NAND has hundreds of layers and packages come in intricate stacks, fresh graduates and veteran engineers alike are being confronted with design challenges that require a rethinking of both classic designs and traditional workflows, but without breaking the laws of physics. “There are pockets of things that have been on 3D for quite some time,” said Kenneth Larson, ... » read more

Four Vertical Power Delivery Architectures For Emerging Packaging and Integration Platforms (UIC)

By Technical Paper Link - 16 Oct, 2023 - Comments: 0

A technical paper titled “Vertical Power Delivery for Emerging Packaging and Integration Platforms – Power Conversion and Distribution” was published by researchers at University of Illinois Chicago. Abstract: "Efficient delivery of current from PCB to point-of-load (POL) is a primary concern in modern high-power high-density integrated systems. Traditionally, a 48 V power signal is con... » read more

Chiplets: Bridging The Gap Between The System Requirements And Design Aggregation, Planning, And Optimization

By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning” was published by researchers at Auburn University. Abstract: "With the availability of advanced packaging technology and its attractive features, the chiplet-based architecture has gained traction among chip designers. The large design space and the lack of sys... » read more

Site-Specific Compositional Info from Periodic Nanostructures Obtained Using Rutherford Backscattering Spectrometry

By Technical Paper Link - 28 Oct, 2022 - Comments: 0

A new technical paper titled "Quantification of area-selective deposition on nanometer-scale patterns using Rutherford backscattering spectrometry" was published by researchers at IMEC and KU Leuven. "We present a site-specific elemental analysis of nano-scale patterns whereby the data acquisition is based on Rutherford backscattering spectrometry (RBS). The analysis builds on probing a larg... » read more

3D Racetrack Memory Device (Max Planck)

By Technical Paper Link - 26 Oct, 2022 - Comments: 0

A new technical paper titled "Three-dimensional racetrack memory devices designed from freestanding magnetic heterostructures" was published by researchers at Max Planck Institute of Microstructure Physics in Halle, Germany. "Magnetic racetrack memory encodes data in a series of magnetic domain walls that are moved by current pulses along magnetic nanowires. To date, most studies have focuse... » read more

Wafer Cleaning Becomes Key Challenge In Manufacturing 3D Structures

By Adele Hars - 20 Oct, 2022 - Comments: 0

Wafer cleaning, once a rather mundane task as simple as dipping wafers in cleaning fluid, is emerging as one of the top major engineering challenges for manufacturing GAA FETs and 3D-ICs. With these new 3D structures — some on the horizon but some already in high-volume manufacturing — semiconductor wafer equipment and materials suppliers in the wet cleaning business are at the epicenter... » read more

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tag: 3D