Rethinking Design, Workflow For 3D

The semiconductor ecosystem is coping with new challenges in the transition to 3D advanced packaging.


In the 3D world, where NAND has hundreds of layers and packages come in intricate stacks, fresh graduates and veteran engineers alike are being confronted with design challenges that require a rethinking of both classic designs and traditional workflows, but without breaking the laws of physics.

“There are pockets of things that have been on 3D for quite some time,” said Kenneth Larson, product management director for the EDA group at Synopsys. “At the same time, there’s a major change and interest in chiplet-based design, as well as stacking for 3D heterogeneous systems. There’s a lot going on right now that’s enabling a lot of new things, but it’s also creating new challenges for engineers.”

Gurtej Sandhu, principal fellow and vice president at Micron, agreed. “It’s a paradigm shift. You now have physics problems at multiple scales. The physics is the same for the device level, but you have to comprehend changes going on in this entire cube to understand how a certain device or a certain part of this cube will be affected, from stress or temperature or other factors that could lead it to not behave normally. In the past, you could ignore such things. When you stack chips, all those things become additive, and they become a problem. How you build models to solve for them and be predictive is a challenge.”

For certain applications, some designers can build on prior experience.

“The designer has experience in 2D design, which is still very much required,” said Keith Felton, product marketing manager at Siemens EDA. “None of it is really obsoleted. Instead they need to apply that knowledge at the 2.5/3D system integration level, because they now have z dimension to interact with and leverage on top of the traditional x and y.”

In some respects, this is less dramatic than technology transitions of the past. “One example of this is when we went from TTL to CMOS logic,” noted Tony Chan Carusone, CTO at Alphawave Semi. “High technology has been evolving quickly for a long time, so it’s bred and attracted people with just the right mix of curiosity and ingenuity and intellectual fearlessness where this doesn’t daunt them.”

Collaboration is key
Still, it’s a confusing world for everyone, especially those new to the field. “Graduates come into a world where, all of a sudden, they have to deal with physical design,” said Chris Mueth, director of new markets development for Keysight. “So when we talk about 2.5/3D, it’s all related to physical design, and that isn’t something that is necessarily taught as regular curriculum. In product teams nowadays, usually it’s a collection of specialists working together. You might have someone who’s good at digital design, another one who’s good at RF power amplifier design, then you have a packaging expert who’s really good at electromagnetics. EDA can make this as seamless as possible for the average engineer, because trying to do electromagnetics together with classical circuit simulation isn’t necessarily a straightforward thing to do.”

A frequent theme in the world of 3D is that the days of silos are over. Everyone has to reach across disciplines and appreciate their colleagues’ expertise and challenges. What could once be passed on as someone else’s problem, has now become everyone’s problem.

Fig. 1: Collaboration becomes more essential as needs converge. Source: Cadence

Fig. 1: Collaboration becomes more essential as needs converge. Source: Cadence

John Park, product management group director in the Custom IC & PCB Group at Cadence, believes everyone’s a system designer with heterogeneous integration. It’s a new world, with many more aspects to consider. “One of the things that’s new is LVS (layout versus schematic). What designers need to do is validate that everything is stacked correctly. Even in 2.5D there’s a stack. You’re putting the die on an interposer, and interposer sits on laminate packets, so every design has multiple tiers to it now. You need a very formal process of validating that everything is aligned properly. So that it can actually be built, you need to validate that conductivity from die one to die two, or chiplet one to chiplet two, or chiplet out to the package pin that interfaces with the board. This process of validating the alignment and conductivity we call system LVS is a brand new thing that package designers need to understand.”

Further, there’s a German expression, “look over your plate,” referring to the need to extend beyond disciplinary boundaries, according to Frank Schirrmeister, vice president of solutions and business development at Arteris. “There is no one person who is the 3D IC engineer. The role of the architect has become even more critical and important. You have this layer of ‘the moderator,’ which is the person who is not an architect per se, the guy who understands everything, but is the person who understands enough of the different disciplines to allow them to interact efficiently.”

Such thinking extends to verification “Some people may believe that they can continue to do the verification, at the chip level, at the boundary,” said Guillaume Boillet, senior director of product management and strategic marketing at Arteris. “The reality is for most of the partitioning, it’s really important that they look at the system holistically, and continue to look at the different components as a whole. For example, with the coherence system across chiplet, there is absolutely no way you can verify your system if you look at different dyes in isolation.”

NAND challenges
3D challenges are also impacting NAND memory, which has become a Jenga-like tower of hundreds of layers.

Micron’s Sandhu said working in 3D requires an open mind, a fundamental quality Micron looks for when it interviews new employees. “For example, we might ask applicants, ‘Do you know what a DRAM is?’ If they don’t, then we ask them to read up on it and come back in two days. We’re looking for how they go about learning.”

That attitude came into play when Micron was trying to scale 2D NAND, but physics kept getting in the way. “You have a certain device size and voltage, it’s going to arc because it’s such a high electric field,” said Sandhu. “But if you can’t reduce the voltage or go any smaller, what do you do? 3D was obviously the direction to go.”

But as Micron discussed its ambitions, veteran engineers pushed back. They had a simple argument: It won’t work.

“It was true,” Sandhu said. “You could not completely reproduce the same performance with the same device in 3D because it’s a different beast. But we had to do it, because the market was demanding it. There’s a paradigm shift that needs to happen around expectations for the device or chip you’re building. We considered chip-to-chip stacking. But there you have the costs of making those two chips, which doesn’t change, plus the extra cost of stacking, so it’s not a cost-effective scaling for the customer. We looked at other ideas, maybe putting a layer on top and so forth. The final version we came up was the highest risk. The material was quite different. It was polycrystalline rather than single crystalline.”

The research and creativity behind that breakthrough led him to comment, “You know that the actual performance will always fall short of what the underlying physics indicates is possible, but it will also never exceed the physics that is possible, and you must know that too.”

Workflow in the world of 3D
All of these considerations are not only design challenges, but can also up-end familiar processes and workflows.

Park noted LVS will require new perspectives. “From a package designer’s perspective, it’s moving from laminate organic substrates to foundry-based substrates, meaning silicon. What is new for package designers is how to design to fit inside something being built at a foundry. That means the design rules to make the device actually yield, and how you go about moving from a very informal sign off process to a very formal process.”

In this new realm of 3D, everything is up for grabs.

“The customer has an established workflow, and they’re already looking at ways they can speed up certain parts of the process, often augmented with AI to, for example, create models that are faster to execute,” said Stephen Slater, EDA product line manager at Keysight. “They’re finding unique and interesting ways to innovate and find more productivity.”

This is necessary given the complexity of designs. “We can have 10 or 20 large systems going into one design,” said Synopsys’ Larsen. “The scale is enormous, and that requires new methodologies. For example, it’s not feasible necessarily to write out a big design, bring it back in, then write it out, and bring it back in. Having a common foundation is becoming very important so you can avoid those things and speed up the engineering productivity. When we are moving from 2D to 3D, being able to do the heterogenous systems in one platform without actually having to do all these in and out, and co-designs that we have done in the past, has become very important.”

Ultimately, a chiplet cannot be designed completely in a vacuum, and the package cannot be designed without knowledge of the chiplets.

“This is because of those multi-physics impacts from power, thermal, mechanical and electrical impacts, which together create a bit of a dichotomy,” said John Ferguson, director of product management at Siemens Digital Industries Software. “The trick is to solve across these domains frequently. Start with the bare basics to help narrow down the best three-dimensional floorplan possibilities. This can be done with dies treated as uniform black-boxes to start. Once an assembly style is selected, more detailed placement decisions can be made as the chiplets become a bit more mature. This process needs to be repeated with each iteration to the full system to ultimately help ensure that final assembly accurately captures the expected electrical behavior.”

Until now, most processes were built on a CMOS process flow, which follows a regular scheme, and devices could be added to the basic framework.

“If you could do that, you had a good chance that you could make the process manufacturable,” said Maarten Rosmeulen, program director at imec. “You could bring it into the fab and get products out. With 3D integration, that process flow architecture is off the table since a lot more different things are possible. We are in a period where we are experimenting with different types of manufacturing paradigms. In a number of years, I think it will settle down to a new set of techniques, much like what CMOS has done for many years, which is a standard framework onto which things are built into.”

Ironically, the newer and more complex the challenges, the more one traditional approach becomes important.

“Because of the additional z-dimension, designers are now working in a hierarchical system,” Siemens’s Felton said. “Just as yesteryear’s craftsman measured twice or thrice and cut only once, you need design tools capable of understanding this new system, its system-level netlist, and the juxtaposition of the elements that make up the system. Everything you then do in design, verification, analysis has to be from the systems perspective, and in 3D. It all must start with early system-level floor-planning of the assembly. With a 2.5D or 3D system, the design’s micro-architect will have multiple configurations or scenarios and choices at hand, and needs to evaluate enough of them to converge on a scenario that will most probably meet PPA and cost targets once implemented. This all needs to be completed using a reasonable level of design fidelity before any detailed implementation take place.”

Hierarchy has many advantages for design as well as for verification, Ferguson said. “The key ingredients for useful hierarchy are to provide an ability for folks to disaggregate design components, allowing them to be designed independently for integration later on; enabling smaller design file hand-off through recognition of repeated structures, i.e. define once and just note unique placement parameters; and, in some cases providing an ability to reduce physical as well as electrical verification times by checking once per repetition versus redundantly. These scenarios don’t always overlap. For example, it is still useful to separate out design components, even if the component in question is only placed once. But in such a case, we’re unlikely to see file size or verification runtime improvements.”

In the move towards a 3D-IC world, a hierarchical design approach — be it bottom-up or top-down, or likely in parallel — has significant value. But there are also new challenges.

“It is still possible to take advantage of hierarchy for things like DRC, LVS and PERC, but there are unique challenges for simulation and timing analysis,” Ferguson added. “This is because each chiplet in an assembly will have its own unique set of impacts from mechanical and thermal effects. Thus, two placements of the exact same chiplet can have very different electrical responses. That brings us back to having to look at each uniquely. There are some approaches that can help, such as capturing the chiplet impacts stand-alone first — for example, using ECXML format for thermal, which may allow redundantly recapturing them at a later state. Unfortunately, so far there is not a similar format for mechanical impacts yet.”

Finally, Tom Daspit, product manager for Siemens EDA, said that for anyone working with current EDA tools, all of this won’t be as daunting as it might first appear. “The 2.5/3D design flow is very similar to the regular full custom design flow. For example, in my layout, I am using designs created by other designers along with my work. I need to understand the size of those designs and the locations of the connections. A full custom layout designer can create a 2.5D design with their current knowledge and tools that they use every day.”

Related Reading
Large-Scale Integration’s Future Depends On Modeling
The progeny of VLSI is 3D-IC and a range of innovative packaging, but all of it has to be modeled to be useful.
True 3D Is Much Tougher Than 2.5D
While terms often are used interchangeably, they are very different technologies with different challenges.
Chiplets: 2023 (EBook)
What chiplets are, what they are being used for today, and what they will be used for in the future.

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