Week In Review: Design, Low Power


Tools & IP Cadence debuted System-Level Verification IP (System VIP), a suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. Tests created using the System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to po... » read more

Understand MOSFET Switch Behavior Via An LED Driver Simulation


Automotive incandescent bulbs have largely given way to more efficient, reliable, stylish, and even safer light emitting diodes (LEDs). LEDs turn on in a fraction of the time and are especially useful in brake lamps, where fractions of a second matter. The challenge in designing an automotive LED lamp is in satisfying government requirements for light output while also being cost effective. Ano... » read more

Power, Reliability And Security In Packaging


Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

Why Chips Are Getting Noisier


In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Moore’s Law Now Requires Advanced Packaging


Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

New Design Approaches At 7/5nm


The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved. There are two fundamental problems. First, there are much tighter tolerances for all of the components in those designs due to proximity effects. Second, as a re... » read more

Taking Inductance And Electromagnetic Effects More Seriously


By Magdy Abadir and Yehea Ismail With increasing frequencies, tighter margins, denser integrated circuits, new devices and materials, the necessity of full EM analysis including magnetic/inductive effects is becoming a fundamental question for the industry. Where and when should full EM verification be included? Can some of major chip failures during development be attributed to ignoring ... » read more

IP Electromagnetic Crosstalk Requires Contextual Signoff


By Magdy Abadir and Anand Raman Continuous advancement in technology scaling is enabling the emergence of high-performance application markets such as artificial intelligence, autonomous cars and 5G communication. These electronic systems operate at multi-GHz speed, while consuming the lowest amount of power possible leaving very little margin for error. Chips in these systems are highly in... » read more

Why Do You Need Chip-Package-System Co-Design And Co-Analysis?


Whether it is the need for sustainable energy, or driving performance while keeping power at bay, or enabling safe and reliable operation of any electronic system, containment of electronic noise — power and signal noise is critical to all of the above. Other factors that impact safe and reliable operation are electromigration (EM), electromagnetic interference (EMI) and mechanical stress ena... » read more

Rethinking Memory


Getting data in and out of memory is as important as the speed and efficiency of a processor, but for years design teams managed to skirt the issue because it was quicker, easier and less expensive to boost processor clock frequencies with a brute-force approach. That worked well enough prior to 90nm, and adding more cores at lower clock speeds filled the gap starting at 65nm. After that, th... » read more

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