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Parasitic Characterization Comes To Power Design Simulation

Discover issues before turning to physical prototypes of switched mode power supplies.

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Two power design challenges are taking teams into unfamiliar territory. Wide bandgap (WBG) semiconductors target greater efficiency and density. Stricter EMI compliance regulations now come standard in mission-critical industries. Power design practices are still catching up. Simulation often takes a back seat to respinning hardware prototypes until success. What’s missing that could make simulation a better option? Parasitic characterization, a technique from RF design simulation now making power design simulation accurate enough to displace respins.

Adding enhanced simulation to the power design workflow is the common theme of two presentations from Keysight Technologies at the upcoming Applied Power Electronics Conference (APEC) 2022 in Houston, March 20-24. The first is an Industry Session on analyzing and optimizing printed wiring board (PWB) effects in switched mode power supplies (SMPS), co-presented with Wolfspeed, a leading silicon carbide (SiC) chip vendor. The second is a Technical Session on using partially saturated inductors (PSIs) in SMPS, co-presented with research teams from two Italian universities. Both draw on the idea of extracting PWB parasitics for simulating performance and EMI.


Parallel SiC Half Bridge layout, courtesy Wolfspeed.

Between the lines, parasitics are more prominent

Historically, analog PWB simulators were driven from the schematic. Interconnects were just lines, without any parasitic elements. Components had performance models matching their primary functions, but again parasitic capacitance and inductance in packaging and on-chip were largely ignored. The RF simulation community, working at higher frequencies, encountered these problems first and built new techniques like 2 ½ D electromagnetic (EM) solvers accounting for layout, dielectric stack-up, vias, packaging, and more.

Faster switching has always been part of the vision for SMPS design. Now, with SiC and GaN parts capable of delivering more power, lower impedance and firmer switching edges enable higher operating frequencies. The side effect is parasitic terms, once swamped by physical impedance terms, now rise to prominence.

Parasitic characterization can get beyond the conventional SPICE simulations that oversimplify models and fall short of accurate results. Keysight PathWave ADS PEPro brings its RF-class EM solver to bear on extracting a coupling matrix, then feeds those parasitics back into a schematic, then simulates the more accurate representation of the PWB in detail.

Wolfspeed, working with industry consultant Dr. Alan Palevsky, teamed with Keysight to show just what exposing parasitics does for results. Their KIT-CRD-HB12N-J1 half bridge delivers 10kW @ 60 kHz using two SiC MOSFETS in parallel on a 4-layer PWB. It forms a building block for synchronous and asynchronous buck and boost SMPS topologies.

A key parameter for Wolfspeed is the VDS  ringing frequency. A physical DUT for the half bridge measured at 65 MHz ringing. Two terms are in the source path: a current probe wire, calculated at 10 nH, and inductance in the layout. In a SPICE simulation, Palevsky had to manually fudge an additional 16 nH of source inductance to match the 65 MHz result. Simulations on a Keysight PathWave ADS PEPro reference design with parasitics extracted matched the 65 MHz ringing.

Wolfspeed and Keysight will explore more simulation results from parasitic characterization at APEC in Industry Session IS19.4 on Thursday, March 24, 9:45am – 10:45am.

Parasitics and PSIs versus EMI analysis

Expanding their EMI curriculum, teams from the University of Cassino and the University of Salerno are digging into Light Load Operation Loss Reduction (LLO-LR) techniques in SMPS design. Normally, worst case operation for EMI considers maximum load conditions. As the name implies, LLO-LR may alter parameters including reducing switching frequency. These changes, intended to maintain efficiency, can worsen EMI.

PSIs can help increase the SMPS density and reduce current ripple under LLO under desaturation, mitigating EMI. It should be no surprise that measuring EMI on physical test setups at various non-maximum load conditions and figuring out exactly where SMPS problems lie might be time-consuming. Capturing what’s happening with a PSI across the load profile can also be difficult. But these scenarios are a perfect use case for simulation – again, using Keysight PathWave ADS PEPro. Automating parasitic extraction for accurate PWB modeling yields true EMI simulation results. PEPro overlays pre-configured EMI compliance profiles on simulation results with a couple quicks, visually showing where results may run into issues in various markets and applications.

The DUT for this effort is a Texas Instruments reference (or evaluation) board, the TI-PMLK BUCK board with its TPS54160 buck regulator. The TP54160 has a pulse skip feature, stretching out the switching duty cycle at lighter loads. By modeling the board in Keysight PathWave ADS PEPro, the researchers observed something interesting via simulation. A few tens of femto Farads of parasitic capacitance from the board can spoof the regulator into pulse skipping at inappropriate times with higher loads. In turn, that leads to unexpected resonance in peak-current controlled regulators and corresponding EMI spikes.


Simplified schematic of TI-PMLK BUCK educational board with TPS54160, courtesy TI.

Spotting that parasitic capacitance on the PWB significantly changes EMI evaluation of this configuration. Professors from the University of Salerno and the University of Cassino will discuss their paper with complete findings at APEC in Technical Sessions – Dialogues D02.1 on Thursday, March 24, 11:30am – 1:30pm.

Re-engaging simulation with better technology

These two studies provide a glimpse of why SMPS design teams should consider adding simulation with parasitic characterization to their workflow. Keysight expertise repurposed from RF design puts better modeling and simulation in reach for power design. Teams who have never simulated, or found it lacking, should re-engage with improved technology. Teams stepping up to wide bandgap SiC or GaN technology will expose parasitics and need better models and simulation to discover issues before turning to physical prototypes.

For more information on APEC 2022 and these sessions:

Applied Power Electronics Conference (APEC)
Houston, George R. Brown Convention Center, March 20-24
Keysight Technologies, Booth 1738



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