Week In Review: Design, Low Power

Chip-level verification; monitoring the chip lifecycle; EMI simulation; GPU IP.


Tools & IP
Cadence debuted System-Level Verification IP (System VIP), a suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. Tests created using the System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to post-silicon bring-up.

Synopsys unveiled its Silicon Lifecycle Management (SLM) platform, which uses embedded monitors and sensors combined with data analytics to optimize SoCs and provide visibility into critical performance, reliability and security issues for the entirety of a chip’s lifespan. The platform’s analytics engines use silicon data-based timing model calibration to minimize required margins and optimize design PPA, reliability and silicon predictability as well as fab and test data to optimize manufacturing yield.

Cadence introduced Clarity 3D Transient Solver, a system-level simulation solution for electromagnetic interference (EMI) system design issues. It is capable of simulating large designs and handles workload levels that require anechoic test chambers to test prototypes for electromagnetic compatibility compliance.

Imagination Technologies uncorked the IMG B-Series of GPU IP. It delivers up to 6 TFLOPS of compute, with an up to 30% reduction in power and 25% area reduction over previous generations. It targets mobile, consumer, IoT, microcontrollers, DTV, and automotive, and contains ISO 26262-capable cores with the IMG BXS.

Samsung Foundry and Synopsys announced a validated automotive reference flow to streamline SoC hardware design for in-system test, implementation, verification, timing and physical signoff for ISO 26262 compliance. The reference flow is targeted for ASIL D autonomous driving and ADAS applications.

Kyocera renewed its license for Arteris IP’s FlexNoC interconnect IP for use as the on-chip communications backbone of its custom SoC powering its flagship enterprise document imaging and management solutions. Kyocera has licensed it since 2016.

Graphcore used Synopsys’ IC Compiler II place-and-route solution for designing its second-generation Colossus MK2 GC200 Intelligence Processing Unit (IPU), which has 59.4 billion transistors on 7nm process technology.

TriEye used Cadence’s Spectre X Simulator to accelerate the design of a next-generation CMOS-based Short-Wave Infrared (SWIR) image sensor. TriEye noted that it observed at least a 2X performance gain over previous simulators while achieving the required accuracy to meet ISO requirements for critical automotive applications.

SiMa.ai adopted products from Synopsys’ DesignWare IP, Verification Continuum Platform, and Fusion Design Platform for the development of its MLSoC, a machine learning platform targeted at specialized computer vision applications. SiMa.ai cited functional safety support for ISO 26262 assessment.

Intel and Synopsys teamed up to implement system-level interoperability between the Synopsys DesignWare Controller and PHY IP for PCI Express 5.0 and future Intel Xeon Scalable processors, providing an end-to-end 32GT/s PCIe 5.0 link.

JEDEC published the JESD403-1 JEDEC Module Sideband Bus standard. SidebandBus was developed in coordination with the MIPI Alliance as both a subset and superset of the MIPI I3C Basic serial bus standard. It defines the parameters for usage of the system management control bus for the coming generation of DDR5 memory modules and enhances I3C Basic with extended commands and functions such as a hub functionality that increases the number of supported devices on the bus.

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