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Week In Review: Design, Low Power


RISC-V RISC-V International announced four new specification and extension approvals. Efficient Trace for RISC-V defines an approach to processor tracing that uses a branch trace. RISC-V Supervisor Binary Interface architects a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode to enable common platform services... » read more

Week In Review: Design, Low Power


Tools, IP, chips Synopsys unveiled a new data-visibility and machine intelligence-guided design optimization solution. DesignDash is complementary to the company's DSO.ai AI-driven design-space-optimization tool and provides a real-time, unified, 360-degree view of all design activities. It uses deep analytics and machine learning to extract and reveal actionable understanding from large amoun... » read more

How To Optimize A Processor


Optimizing any system is a multi-layered problem, but when it involves a processor there are at least three levels to consider. Architects must be capable of thinking across these boundaries because the role of each of the layers must be both understood and balanced. The first level of potential optimization is at the system level. For example, how does data come in and out of the processing... » read more

Choosing Which Tasks To Optimize In Chips


The optimization of one or more tasks is an important aspect of every SoC created, but with so many options now on the table it is often unclear which is best. Just a few years ago, most people were happy to buy processors from the likes of Intel, AMD and Nvidia, and IP cores from Arm. Some even wanted the extensibility that came from IP cores like Tensilica and ARC. Then, in 2018, John Henn... » read more

Domain-Specific Design Drives EDA Changes


The chip design ecosystem is beginning to pivot toward domain-specific architectures, setting off a scramble among tools vendors to simplify and optimize existing tools and methodologies. The move reflects a sharp slowdown in Moore's Law scaling as the best approach for improving performance and reducing power. In its place, chipmakers — which now includes systems companies — are pushing... » read more

Week In Review: Design, Low Power


Intel intends to take Mobileye public in mid-2022 on a US market through an IPO of newly issued stock. The subsidiary, which Intel acquired in 2017, develops SoCs for ADAS and autonomous driving solutions. Mobileye has achieved record revenue year-over-year with 2021 gains expected to be more than 40 percent higher than 2020, highlighting the powerful benefits to both companies of our ongoing p... » read more

Week In Review: Design, Low Power


Business Synopsys acquired Concertio, a provider of AI-powered performance optimization software. The acquisition will bolster Synopsys' silicon lifecycle management platform SiliconMAX SLM with the addition of Concertio's autonomous software agent that, when installed on the target system, continuously monitors the interactions between operating applications and the underlying system enviro... » read more

Week In Review: Design, Low Power


The UK's Competition and Markets Authority is raising new challenges for Nvidia's proposed acquisition of Arm, suggesting in a new report that an in-depth Phase 2 investigation into the deal is warranted on competition grounds. Andrea Coscelli, chief executive of the CMA, said, “We’re concerned that Nvidia controlling Arm could create real problems for Nvidia's rivals by limiting their acce... » read more

Merging Verification And Test


While the disciplines of functional verification and test serve different purposes, their histories were once closely intertwined. Recent safety and security monitoring requirements coupled with capabilities being embedded into devices is bringing them closer together again, but can they successfully cooperate to bring about improvements in both? Getting there may be difficult. Three phases ... » read more

Making Sense Of New Edge-Inference Architectures


New edge-inference machine-learning architectures have been arriving at an astounding rate over the last year. Making sense of them all is a challenge. To begin with, not all ML architectures are alike. One of the complicating factors in understanding the different machine-learning architectures is the nomenclature used to describe them. You’ll see terms like “sea-of-MACs,” “systolic... » read more

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