Interface IP in 3D; SOCAMM in data centers; edge intelligence implementations; deposition, etch for 3D; interconnect telemetry; design–manufacturing collaboration.
Synopsys’ Madhumita Sanyal shows why interface IP has emerged as the keystone for building scalable, reliable 3D multi-die designs in which interconnects often have a greater influence on overall system capability than the peak performance of individual dies.
Cadence’s Frank Ferro checks out why SOCAMM2 built on LPDDR is being deployed in AI data centers, increasing memory bandwidth and capacity while at the same time consuming less than half the power of traditional DDR configurations.
Siemens’ John Soldatos, Samir Jaber, and Jake Hertz examine how edge intelligence is being implemented across real systems and why processing capabilities, memory architecture, connectivity, power management, and component availability all play a role in determining how edge systems are built and scaled.
Lam Research’s Vahid Vahedi highlights the importance of advanced deposition and etch capabilities in creating 3D memory and logic structures with taller structures, perpendicular processing, and smaller features.
Arm’s Jumana Mundichipparakkal suggests that while processor telemetry remains essential, it is no longer enough on its own to handle the complex shared fabric requests must travel through in modern devices, and introduces a structured interconnect telemetry approach to analyze system-level performance.
Imagination’s Ke Xu considers pairing RISC-V CPUs with GPUs to enable high-performance SoCs for intelligent edge devices.
Keysight’s Alan Wadsworth explains why an electronic load is a more efficient solution to test power sources than using a fixed value resistor and outlines some of their limitations.
The ESD Alliance’s Bob Smith chats with Qualcomm’s Lu Dai about industry collaboration and what it will take for a seamless automated flow between design, manufacturing, and packaging.
For a change of pace from reading, why not watch a recent video:
Benefits and questions surrounding a next-gen low-power standard for high-performance compute in New CPU Memory Module.
System-in-Package Challenges and the engineering considerations in multi-chiplet designs.
Why Proof Convergence Matters and how to leverage patterns in formal verification to reach sign-off faster.
General-purpose processing demands will multiply once machines are talking to machines, which is Why More CPUs Are Needed For Agentic AI.
The State Of The Market For Edge Silicon and what makes one AI chip better than another.
Why new LPDDR releases make them the choice Memory For AI At The Edge.
How AI Will Automate Chip Design, with a step-by-step application of AI in EDA.
Improving Yield Through Shared Data argues the case for sharing test, manufacturing, and design data.
New Challenges In Signoff and what else to consider before sending a design to manufacturing.
The New Performance Requirements For Audio and why audio interactions with machines drive increasing demand for better sound quality.
What’s behind the widespread adoption of extremely high-throughput wireless as Wi-Fi 7 Moves To The IoT.
Changes In Chip Architectures At The Edge and how to build an efficient and flexible multi-die system for edge AI.
And don’t miss the seven-part deep dive into how AI is being used in semiconductor manufacturing:
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