Leveraging patterns in formal verification to reach sign-off faster.
Achieving a deterministic “yes or no” answer in semiconductor verification is becoming more challenging as chip complexity increases. There are more cores, more potential interactions, and more reliance on AI to build AI chips. Ashish Darbari, CEO of Axiomise, talks about the impact of functional interactions involving safety and security, and where to look for common patterns to prevent bugs from creeping into these designs, and how this all can be used to reduce time to sign-off with higher coverage.
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