Verification Convergence: Problem Definition

A while ago, I had to go to the ER with my friend who suddenly had a numb feeling in his face. He felt okay (and everything else is okay with him), but better be safe than sorry. While the doctor examined him I noticed that before tracing the problem itself, she asked some questions to rule-out a problem she was already familiar with and that can manifest itself in similar ways. Only then, a... » read more

IoT Debugging Crosses The Hardware-Software Divide

By Paul Hill and Gordon MacNee Debugging is an important part of embedded design; one that necessarily crosses the hardware/software divide. At a system level, the functionality of an embedded design is increasingly defined by firmware, so avoiding bugs requires engineers with specific disciplines to work closely together during the design phase of a project. It can also mean resisting the u... » read more

Utilizing More Data To Improve Chip Design

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

How To Build Functional Safety Into Your Design From The Start

The focus on functional safety IP is rapidly growing and we’re seeing this growth not just in automotive but in many other markets including, avionics, medical, industrial and railways, where systems need to efficiently identify and mitigate the occurrences of faults, and where more confidence is required with respect to the design practises employed for the development of IP. Currently, m... » read more

Getting A Handle On RTL X-Verification Challenges

The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout.  Some engineers point out that we have always had to deal with X’s and nothing has really changed. In fact, today’s SoC employ different power management schemes that wake-up or suspend IP.  As any designer knows, when powering ... » read more

When Order Matters

Do you brush your teeth before dinner? Put on your shoes before going to bed? Iron your clothes before you wash them? Okay, forget that last one. No one irons clothes anymore…do they? Anyway, my point is, if you want to achieve the best results from a process, order can be really important. And so it is with double patterning (DP) error debugging. As I’ve discussed, there are many types ... » read more

The Other Side Of Formal

It’s natural to think of formal analysis as a ruthlessly effective bug hunter and verification tool. But as the following case study from Homayoon Akhiani, presented at the Jasper Users Group (JUG) meeting shows, customers are using this approach to increase their SoC’s performance in ways that are very visible to the end-user of the part. Such visible improvements — in this case, minimiz... » read more

What You Can Learn From Robots

My sons are in the robotics club at their high school. They program a small robot to perform simple tasks to score points in a competition. It’s a great way for them to learn about embedded systems and stimulate their interest in technology. While looking for ways to help them improve their understanding of embedded systems we started going through some of the online material, one of the c... » read more

The Growing Verification Challenge

As complexity continues to mount in designing SoCs, so does the challenge of verifying them within the same time window and using the same compute and engineering resources. Chipmakers aren’t always successful at this. In many cases they have to put more engineers on the verification and debug at the tail end of a design to get it out the door on or close to schedule. In many cases that al... » read more

Tech Talk: Dealing With The Unknowns

Rebecca Lipon, senior product marketing manager for verification at Synopsys, discusses the problematic X's and where verification teams typically make mistakes in trying to eliminate the false X's from their designs. Power emerges as the biggest problem. [youtube vid=Iym4ITWJJrs] » read more

← Older posts