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Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity

Finding and fixing errors efficiently by using coding assistance for SystemVerilog.

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The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project stage multiplies the cost by ten. Bugs that escape verification and make their way to silicon are very expensive and time-consuming to fix. The ideal is to catch as many types of issues as possible as the designers enter the register transfer level (RTL) design and the verification engineers code the testbench in a hardware verification language (HVL). Today, both groups are most likely to use SystemVerilog as their input format.

The hardware design and verification process looks much like software development, with the engineers writing, testing and debugging code. Given that coding assistance tools have existed for programming languages for years, it might seem easy to develop a similar solution for SystemVerilog. However, it is an extraordinarily complex language with RTL constructs, assertions, support for constrained-random testbenches and object-oriented programming (OOP) capabilities. Just parsing the full language and checking for proper syntax is a significant effort, but much more is needed to have the desired “shift left” in development by finding and fixing many types of bugs.

The SystemVerilog code must be fully compiled and elaborated, allowing all parts of the design and testbench to be connected and enabling complex checks. Pseudo-synthesis is also required to analyze signals on the bit level, detect dead code, and recognize clocks and resets. Ideally, the parsing, compilation, elaboration, and synthesis all happen “on the fly” so that checking occurs every time the user types in new code or edits existing code. An easy-to-use interactive editing and exploration interface must be backed by powerful language engines that immediately run the checks, report the results and suggest “quick fixes” when possible.

This process must be resilient in the presence of coding errors, critical for running early in development when the design and testbench are incomplete. In the interactive interface, errors and warnings from the checks are marked directly on the relevant sections of the code. The user can have multiple views open at the same time, all hyperlinked. Clicking on an error or warning in a problem report window navigates directly to the relevant code in the relevant file. The checked rules must be configurable, on a per-user, per-project or company-wide basis, to enforce a consistent coding style. Users must be able to add custom rules and waive warnings when appropriate.

An effective checking solution for chip design and verification code must meet additional requirements. It must support the complete SystemVerilog language and have built-in knowledge of the Universal Verification Methodology (UVM). This provides great benefit for verification teams as they write and debug testbenches. Checks must include detection of unreachable (dead) code, infinite loops and recursions, null class handles, dynamic casting violations, data type mismatches, out-of-bounds accesses, “unique” case violations, and errors in constraints and assertions. Other checks ensure code compliance with popular simulation, emulation, and debug solutions.

It is far more efficient to find and fix issues during coding than by debugging testbench simulation failures. Simulation cannot begin until most or all of the testbench and design is ready, but code checking finds these problems much earlier in the project. In many cases, it not only reports a problem, but also makes a quick fix suggestion. If the suggestion is accepted, code is generated with as much information as possible filled in and a “TODO” comment added where user input is needed. The rules to be checked can be shared among team members and enforced across projects and organizations.

The built-in rules must check UVM testbench code for compliance with the IEEE 1800.2 standard and for other types of errors. The deep understanding of the UVM enables advanced checks and quick fix suggestions for problems. Templates for many common constructs are provided, and these can be extended by users with custom templates. Many UVM components are quite complex, so adding them from a blank editing screen is tedious and error prone. As soon as the verification engineer starts typing in code, for example to define a new class, a template provides guidance to complete all information needed.

There must be additional assistance to make writing code faster, easier, and more accurate. When the user starts to type in a name, auto complete offers a list of already defined names that could match. It is more efficient to select from a list than to type in a long name. Content assist displays relevant options, for example the available members for a chosen class. The user can select one of these members and use it as a template. Any new names defined during this process, as well as name changes in general, can be propagated automatically across all relevant files. It is not necessary to manually iterate through the files making the same changes to each one.

Early code checking also has many benefits for designers. Many of the capabilities for testbenches are also relevant for RTL design code, including compilation and elaboration checks, synthesis checks, customizable rules, dead code and out-of-bounds access detection, case violations, quick fix suggestions, auto complete, and content assist. Design-specific checks detect coding errors and practices that may compromise proper operation. These must include combinational loops, unintended latches, ungated flip-flops, clock and reset issues, driver/load violations and width mismatches. The designer may accept suggested fixes or waive warnings.

The Synopsys Euclide solution meets all these requirements. Code viewing and navigation options make it easier to understand inherited designs and testbenches. SystemVerilog beginners learn the language more quickly, and even experienced engineers benefit from quick fixes and code templates. On the fly checks detect many types of errors at the source, improving code quality. Common coding style and methodology can be enforced project wide to make design and testbench integration easier. The result is increased engineering productivity, shorter project schedules and decreased chances of chip turns due to missed bugs.

For more information, a white paper is available.



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