Helping the debugging process of HW-SW co-verification by providing better visualization.
In every complex SoC verification process, it is necessary to activate the CPUs during verification and to check the operation of the software they execute alongside the test’s scenarios. At a minimum, basic scenarios such as “boot rom execution” are tested, but in many cases, further scenarios are required. The CPUs themselves are usually proven IPs, but in order to verify their integration and operation within the SoC, it is not enough to connect a VIP to the CPU bus and have it imitate the CPU’s behavior.
Cogita helps the debugging process of HW-SW co-verification by providing better visualization, thus insight into the execution that takes place by the CPUs and its relation to what is going on inside the UVM testbench. As we will see in this case, Cogita machine learning capabilities also come in very handy in such cases.
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