tag: SoC verification

Hardware-Software Co-verification (ARM CPU)
By Vtool - 26 May, 2021 - Comments: 0

In every complex SoC verification process, it is necessary to activate the CPUs during verification and to check the operation of the software they execute alongside the test’s scenarios. At a minimum, basic scenarios such as “boot rom execution” are tested, but in many cases, further scenarios are required. The CPUs themselves are usually proven IPs, but in order to verify their integrat... » read more

Accelerating SoC Verification Closure With Unified Verification Management Solution
By Synopsys - 08 Feb, 2021 - Comments: 0

Functional verification of system-on-chip (SoC) designs requires best-in-class tools linked together in a unified solution in order to address exponential complexity challenges. There is no one-size-fits-all method for verification. Complex designs require a combination of virtual prototyping, static checks, formal analysis, simulation, emulation and FPGA prototyping. The execution of all the t... » read more

A UFS Verification Closure Flow Using The Synopsys Verification Continuum Platform
By Synopsys - 11 Dec, 2019 - Comments: 0

It's a longstanding cliche, but it is true that “there is no silver bullet for functional verification.” No single tool or methodology can find and shoot down all the bugs in a large, complex semiconductor design. Simulation is well understood but can be slow for today's large SoCs. Emulation hardware is fast, but expensive enough that it is usually shared across a verification team. Formal... » read more

User Case Study: Using Formal To Verify Low Power Functionality And Eliminate Unwanted ‘Xs’
By Joseph Hupcey III - 10 Apr, 2014 - Comments: 3

The cynics among us might argue that the addition of low power circuitry is a clever scheme by the energy industry to cause an equal amount of power to be consumed by low power verification as is saved by end-user usage.  As if modern SoC verification wasn’t challenging enough, the addition of low power can create corner cases that can escape even the most well-written UVM testbenches.  Ind... » read more

Is Verification At A Crossroads?
By Ann Mutschler - 27 Feb, 2014 - Comments: 1

As SoC verification methodologies and technologies have continued to mature, it’s an interesting time for engineering teams as they look to meet time to market goals and cut costs in an environment of cutthroat profit margins. Whether it is hardware emulation, FPGA prototyping, virtual prototyping or traditional software simulation, each platform has its strengths and drawbacks, with overl... » read more

Start Verification Early To Avoid Pitfalls Later
By Ann Mutschler - 24 Oct, 2013 - Comments: 1

It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made. Harry Foster, chief scientist for v... » read more

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