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A UFS Verification Closure Flow Using The Synopsys Verification Continuum Platform

How Synopsys Verification Continuum Platform can be used to verify a real-world design.

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It’s a longstanding cliche, but it is true that “there is no silver bullet for functional verification.” No single tool or methodology can find and shoot down all the bugs in a large, complex semiconductor design. Simulation is well understood but can be slow for today’s large SoCs. Emulation hardware is fast, but expensive enough that it is usually shared across a verification team. Formal techniques are potentially exhaustive, but often limited in capacity. System-on-chip (SoC) designs add multiple layers of software to the traditional hardware verification challenges. The industry uses more than a dozen languages and formats for verification: SystemVerilog, VHDL, C/C++/SystemC, Property Specification Language (PSL), the Open Verification Library (OVL), Unified Power Format (UPF), Tcl, PERL, JAVA and more. The Universal Verification Methodology (UVM) covers simulation testbenches very well but does not address all tools and techniques.

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