tag: debugging

Getting A Handle On RTL X-Verification Challenges
By Graham Bell - 27 Mar, 2014 - Comments: 1

The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout.  Some engineers point out that we have always had to deal with X’s and nothing has really changed. In fact, today’s SoC employ different power management schemes that wake-up or suspend IP.  As any designer knows, when powering ... » read more

When Order Matters
By David Abercrombie - 20 Mar, 2014 - Comments: 0

Do you brush your teeth before dinner? Put on your shoes before going to bed? Iron your clothes before you wash them? Okay, forget that last one. No one irons clothes anymore…do they? Anyway, my point is, if you want to achieve the best results from a process, order can be really important. And so it is with double patterning (DP) error debugging. As I’ve discussed, there are many types ... » read more

The Other Side Of Formal
By Joseph Hupcey III - 13 Feb, 2014 - Comments: 1

It’s natural to think of formal analysis as a ruthlessly effective bug hunter and verification tool. But as the following case study from Homayoon Akhiani, presented at the Jasper Users Group (JUG) meeting shows, customers are using this approach to increase their SoC’s performance in ways that are very visible to the end-user of the part. Such visible improvements — in this case, minimiz... » read more

What You Can Learn From Robots
By Jon McDonald - 30 Jan, 2014 - Comments: 0

My sons are in the robotics club at their high school. They program a small robot to perform simple tasks to score points in a competition. It’s a great way for them to learn about embedded systems and stimulate their interest in technology. While looking for ways to help them improve their understanding of embedded systems we started going through some of the online material, one of the c... » read more

The Growing Verification Challenge
By Ed Sperling - 30 Jan, 2014 - Comments: 1

As complexity continues to mount in designing SoCs, so does the challenge of verifying them within the same time window and using the same compute and engineering resources. Chipmakers aren’t always successful at this. In many cases they have to put more engineers on the verification and debug at the tail end of a design to get it out the door on or close to schedule. In many cases that al... » read more

Tech Talk: Dealing With The Unknowns
By Ed Sperling - 15 Jan, 2014 - Comments: 0

Rebecca Lipon, senior product marketing manager for verification at Synopsys, discusses the problematic X's and where verification teams typically make mistakes in trying to eliminate the false X's from their designs. Power emerges as the biggest problem. [youtube vid=Iym4ITWJJrs] » read more

printf(“I Like”);
By Achim Nohl - 26 Jul, 2012 - Comments: 0

By Achim Nohl Debugging software by adding printf statements in the code is not considered the cleanest and most advanced debugging approach, but when you are searching for the root cause of a problem you often look to the debugging method you are most familiar with and can apply easily. The hurdle of setting up a complex debug or trace tool is counterproductive when dealing with schedule c... » read more

Redefining ‘Good Enough’
By Ed Sperling - 24 Jun, 2010 - Comments: 0

The increasing amount of software content in devices and the ability to add fixes after tapeout is changing the definition of what’s considered a market-ready product. This is business as usual in the software world, where patches upon patches are considered routine. Service packs are a way of fixing problems when millions of lines of code interact with millions more lines of code in unan... » read more

Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy