Blog Review: Mar. 4

Cadence’s Subash Peddu digs into the challenge of balancing performance, power efficiency, SoC layout optimization, and futureproofing when defining SoCs and memory subsystems for tomorrow’s AI accelerators.

Siemens’ Nicolae Tusinschi suggests that formal verification isn’t just about finding bugs, and the ability to achieve mathematical certainty can fundamentally change how hardware design and verification are approached.

Synopsys’ Catherine Le Lan highlights the tape out of a 7nm AI chip by ETH Zurich and Technical University of Munich as part of an effort to advance all-European HPC accelerator technology.

Imagination’s Ed Plowman warns that power and the associated thermal constraints, rather than area and transistor count, are the limiting factors in the sub‑2nm era that will shape GPU IP, SoC integration, and architectural trade‑offs for the next decade.

Lam Research’s Brett Lowe finds that while virtual design of engineering and predictive modeling can expose integration risks early, their value depends on accurate process models calibrated to real fab behavior, with strong correlations between model inputs and measurable outputs.

Arm’s Odin Shen shows how to build a fully offline, real-time voice assistant that delivers low-latency, human-like dialogue without sending data outside the local environment by using the Arm-based NVIDIA DGX Spark platform and open-source components such as faster-whisper and vLLM.

Keysight’s Christian Loew explains battery internal resistance testing, measurement methods, and how it helps in understanding a battery’s quality, current state, and performance

SEMI’s Anshu Bahadur and Mark da Silva observe that edge AI deployed directly on fab tools, sensors, and local controllers is shifting from experimental to essential, with leading manufacturing systems that integrate hundreds of sensing channels exposing the limits of traditional, centrally managed control.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology editor Brian Bailey considers which companies will lead the integration of AI with EDA.

Axiomise’s Fabiano Muto explains why verification speed without provable correctness is not progress.

Synopsys’ Robert Kruger outlines how chiplet IP is changing to accommodate the requirements of multi-die design, with 7 benefits.

Arteris’ Ashley Stevens digs into AI chiplets and why clarity at the architectural and semantic layers is needed to optimize efficiency.

Siemens EDA’s Daniel Zhang and Modelwise’s Claudius Jordan explore automated functional safety, demonstrating simulation and FMEDA analysis of a voltage monitor circuit.

Cadence’s Veena Parthan shows how a synchronized virtual replica of a data center enables capacity planning, reduces stranded capacity, and supports specialized deployments.