How IP Subsystems For Chiplets Will Unlock Your Next Wave Of Innovation

After many years of hope, promises, and commercial challenges, a robust environment that supports multi-die design is now taking shape. These events represent a sea of change for semiconductor design and manufacturing when compared to the traditional single-die monolithic design approach. Moore’s Law drove these original and substantial monolithic design accomplishments. But the massive requirements of ever-increasing AI workloads demand a new approach to chip design. As we move from Gen AI to multi-modal applications and agentic orchestration, the growing data processing, model complexity, and latency expectations require purpose-built, custom silicon. This new class of design goes well beyond what can be delivered with monolithic SoCs. The only way to deliver this complexity is with a multi-die design approach.

Fig. 1: Pushing beyond the limitations of Moore’s Law.

Monolithic scaling once gave us a near‑doubling of density and frequency each generation, with stable power at iso‑frequency. Such scaling has slowed significantly, while AI’s appetite for parameters, activations, and interconnect explodes. The industry’s response is to split compute, memory, and I/O across dies, XPU chiplets are pushing toward the reticle limit, and stitch it all together with high‑bandwidth, energy‑efficient die‑to‑die interconnect. The industry goal now is trillion‑transistor systems realized through multi‑die design. This tight coupling of multiple dies in a single package helps to address interconnect delay limitations and reduce power consumption as compared to multi-package approach on a PCB.

There is substantial innovation underway to facilitate the partitioning, design, integration, and verification of complex multi-die designs. Here is a great source of information on this work. This article focuses on how IP reuse is changing to accommodate the requirements of multi-die design. We will explore the special considerations for items such as interface IP and the impact IP subsystems and chiplets (defined as dies) can have on this new and emerging design style. A well-planned chiplet strategy can have a profound impact on success. But an effective chiplet strategy has many dimensions. Let’s examine the requirements.

The journey from IP to chiplet

Design partitioning has always been an important part of any complex semiconductor design project. Partitioning informs what functions comprise the fundamental building blocks of the design and how those blocks should be combined to form larger subsystems. In a multi-die design, the partitioning step is complicated by the need to account for latency, power, and physical constraint tradeoffs that depend on how functions are distributed across dies.

It is useful to define what we mean by “chiplet”. Chiplet is the collection of information that defines a small, modular integrated circuit that can be integrated in a single package to create a multi-die design. Anywhere from a few chiplets to over 50 chiplets can be included in a single package. Unlike traditional monolithic chips, which integrate all functionalities into a single silicon die, chiplets break down these functionalities into smaller, specialized dies. These chiplets are then interconnected within a single package, resulting in a multi-die design allowing for greater flexibility, efficiency, and scalability.

Chiplets can be implemented as either 2D dies or 3D stacked dies. Compute functions are typically built on the most advanced process technologies, while I/O and memory are often implemented on N‑1 or N‑2 nodes to reduce cost, particularly for analog and memory functions that do not scale efficiently on smaller, more expensive geometries. Figure 2 illustrates the incredible rise in the use of chiplets for multi-die design. This IBS research predicts that more than half of design starts below 7nm will be chiplet-based by 2030.

Fig. 2: Growing adoption for chiplets to address AI workloads.

Figure 3 illustrates that an AI multi-die design can comprise a hierarchical architecture with as many as 50 or more chiplets with functions that include:

Fig. 3: AI multi-die design example.

A system like this poses many engineering challenges. Some are design-related, others require collaboration across the semiconductor ecosystem to ensure quality, reliability, and conformance to standards. Some of these items are familiar from monolithic design requirements, but they represent a new level of analysis and validation across potentially heterogeneous and dispersed sources of IP. Some, such as packaging requirements for power and thermal management, are new and will be influenced by novel materials that must be sourced and proven in a production setting.

Chiplet choices can have a significant impact on the quality and cost of the final design. The ability to have a clear picture of all parameters of the chiplets under consideration will be critical to implement a shift-left strategy during early design. This will be a key factor to ensure a predictable path from A0 to production ramp. Figure 4 illustrates some of the key considerations that will need to be tracked and analyzed.

Fig. 4: Engineering challenges and considerations for the use of chiplets.

Chiplets deliver far more degrees of freedom than the IP that is used in monolithic design. Chiplets can be combined to form many types of subsystems. And these subsystems can be integrated in a variety of ways to form a multi-die design. This creates the need for accurate characterization and complete design and test specifications to be delivered with chiplets to ensure the system can perform as intended.

This level of accuracy and detail will strain the existing ecosystem.  Add to this the growing list of evolving standards that must be tracked and supported and the problem gets even larger.  Critical enabling standards for multi-die design such as 40G/64G UCIe, UALink, Ultra Ethernet, PCIe 7.0, DDR5, LPDDR6/5X/5, and HBM4 are examples of protocols in data center/AI applications. Next, we will examine the benefits of IP subsystems for chiplets.

The motivation and benefits of IP subsystems for chiplets

The IP subsystem approach brings substantial advantages for multi-die designs, where integration complexity, performance, and reliability are critical. Below are some of the considerations and benefits of this approach.

Simplified integration of heterogeneous dies: In a multi-die design, each die can come from different process nodes or even vendors. An IP subsystem bundles multiple tightly coupled IP blocks (e.g., controller, PHY, firmware, test logic) into a validated unit with a well-defined interface. This approach reduces system-level integration effort and design risk. This reduction is realized through effects such as the minimization of inter-die protocol mismatches (e.g., UCIe). Verification is also simplified since the IP subsystem is pre-verified as a single unit.

Proven interoperability and validation: Multi-die designs demand interoperability across heterogeneous dies. The use of silicon-proven and pre-verified IP subsystems in realistic multi-die configurations reduces design time and risk. Bring-up time is also shortened since the IP subsystem typically includes validated firmware and test suites. Overall, the number of potential integration issues at the system level is reduced.

Performance optimization: Because an IP subsystem can integrate multiple functional components (e.g., memory controller, compute logic, interconnect, and power management), performance and power are easier to co-optimize. For example, latency and bandwidth can be balanced across die boundaries, and high-speed die-to-die interfaces can be optimized.  All this can focus on tuning for specific workloads (e.g., AI, networking, storage).

Reduced design complexity and time-to-market: A complete pre-verified IP subsystem accelerates design closure by providing ready-to-use IP clusters vs. piecing together IP blocks and verifying results. This approach reduces design team workload in integration, floorplanning, and verification. The team can focus on system differentiation instead of configuring and validating lower-level IP blocks.

Opportunity to leverage built-in testability and reliability features: Multi-die designs present debug and test challenges due to package-level interconnects and possibly the lack of external pin connections to individual chiplets. IP subsystems typically include integrated DFT (design for test), monitoring, and health-check capabilities and hierarchical test servers. Advanced capabilities such as lane test and repair for die-to-die connections can also be included. This is essential for yield and reliability in multi-die designs. Pre- and post-package test is facilitated, while improving yield and reliability with embedded self-test and repair capabilities. This approach can also embed in-field diagnostics, which are very useful to monitor and analyze interfaces.

Built-in security: Given the substantial rise in sophisticated AI-fueled hardware attacks, strong and verified security must be part of all new semiconductor designs. Ensuring the appropriate level of protection and security can be challenging in a multi-die setting where devices can be sourced from multiple providers. Leading IP vendors are addressing these requirements with pre-verified interface IP subsystems that offer authentication and data encryption as part of the IP subsystem. Support for post-quantum cryptography (PQC) is essential in many applications to address threats long term.

Ecosystem alignment enables futureproofing: Leading IP vendors are also maintaining IP subsystem compatibility with most widely used standards, including UCIe, CXL, PCIe, UAL, Ultra Ethernet, and other interface standards. It also means keeping pace with a growing number of chiplet consortiums and interoperability efforts from organizations like OCP, ASRA and IMEC, Chassis, and others. This ensures future interoperability across vendors and foundries and provides a scalable baseline for next-generation designs. Re-use across multiple products and architectures is facilitated as well. Table 1 summarizes the significant benefits of using pre-verified IP subsystems.

Table 1: Pre-verified IP subsystem benefits.

Closing: Convergence is a choice

Chiplets are not a detour from the traditional SoC path; they are a force multiplier built on the same foundations. Whether you build ASICs, ship ASSPs, or develop bespoke designs, the playbook is the same: define the boundary, prove it in layers, and only assemble what you already know is good – including leveraging pre-verified, configurable IP subsystems. And as discussed, applying these same concepts to chiplets will have significant benefits.

Synopsys offers the broadest IP portfolio for interface, processor, security, and foundation IP. With over 260 IP subsystems in customer designs, Synopsys helps customers design chiplets with confidence. To help overcome multi-die integration challenges, Synopsys offers a comprehensive and scalable multi-die solution, encompassing EDA and IP products. The solution helps with fast heterogeneous integration from early architecture to manufacturing. Synopsys collaborates with leading foundries with certified AI-powered EDA flows and high-quality IP on the most advanced process technology, while enabling advanced packaging technology.

Check out Synopsys’ Multi-Die Design Start Guide to get a jump start on your next project.