Performance and Power Tradeoffs At 7/5nm


Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Making Chips To Last Their Expected Lifetimes


Chips are supposed to last their lifetime, but that expectation varies greatly depending upon the end market, whether the device is used for safety- or mission-critical applications, and even whether it can be easily replaced or remotely fixed. It also depends on how those chips are used, whether they are an essential part of a complex system, and whether the cost of continual monitoring and... » read more

Week In Review: Design, Low Power


Tools & IP Cadence debuted System-Level Verification IP (System VIP), a suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. Tests created using the System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to po... » read more

Reliability Over Time And Space


The demand for known good die is well understood as multi-chip packages are used in safety-critical and mission-critical applications, but that alone isn't sufficient. As chips are swapped in and out of packages to customize them for specific applications, it will be the entire module that needs to be verified, simulated and tested, and analyzed. This is more complicated than it sounds for s... » read more

From Design To Deployment: How Silicon Lifecycle Management Optimizes The Entire IC Life Span


The beginning of the IC journey gets most of the attention in the semiconductor world – the challenges of design, test and manufacturing. But the reality is the entire lifecycle of a chip needs attention, requiring ways to ensure a chip’s intended and ongoing operation, especially in ever-changing operating environments where chips ultimately reside. The growing complexity of today’s e... » read more

IGBT Power Cycling And Lifetime Testing


I have never been very good at introducing topics. During my presentations, I either jump directly into the subject matter, or start with a joke. My mom always said I could be a stand-up comedian. I prefer to sit. Oddly, that led me to becoming an engineer. And while this introduction does not lead me any closer to my actual topic, I presume some people rolled their eyes back and crossed their ... » read more